Merge git://www.denx.de/git/u-boot-marvell

Conflicts:
	arch/arm/Kconfig

Signed-off-by: Tom Rini <trini@konsulko.com>

5 files changed, 14 insertions, 46 deletions

diff --git a/board/Marvell/db-88f6820-gp/Kconfig b/board/Marvell/db-88f6820-gp/Kconfig
deleted file mode 100644
index f12b96829d..0000000000
--- a/board/Marvell/db-88f6820-gp/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_DB_88F6820_GP
-
-config SYS_BOARD
-	default "db-88f6820-gp"
-
-config SYS_VENDOR
-	default "Marvell"
-
-config SYS_CONFIG_NAME
-	default "db-88f6820-gp"
-
-endif
diff --git a/board/Marvell/db-88f6820-gp/kwbimage.cfg b/board/Marvell/db-88f6820-gp/kwbimage.cfg
index cc05792556..1f748db37c 100644
--- a/board/Marvell/db-88f6820-gp/kwbimage.cfg
+++ b/board/Marvell/db-88f6820-gp/kwbimage.cfg
@@ -9,4 +9,4 @@ VERSION		1
 BOOT_FROM	spi
 
 # Binary Header (bin_hdr) with DDR3 training code
-BINARY spl/u-boot-spl.bin 0000005b 00000068
+BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068
diff --git a/board/Marvell/db-mv784mp-gp/Kconfig b/board/Marvell/db-mv784mp-gp/Kconfig
deleted file mode 100644
index 428a5e1516..0000000000
--- a/board/Marvell/db-mv784mp-gp/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_DB_MV784MP_GP
-
-config SYS_BOARD
-	default "db-mv784mp-gp"
-
-config SYS_VENDOR
-	default "Marvell"
-
-config SYS_CONFIG_NAME
-	default "db-mv784mp-gp"
-
-endif
diff --git a/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c b/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c
index d7aa1499ad..9305284117 100644
--- a/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c
+++ b/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c
@@ -87,40 +87,32 @@ int board_eth_init(bd_t *bis)
 	return pci_eth_init(bis);
 }
 
-#ifdef CONFIG_RESET_PHY_R
-/* Configure and enable MV88E1545 PHY */
-void reset_phy(void)
+int board_phy_config(struct phy_device *phydev)
 {
-	u8 phy_addr[] = CONFIG_PHY_ADDR;
-	u16 devadr = phy_addr[0];
-	char *name = "neta0";
 	u16 reg;
 
-	if (miiphy_set_current_dev(name))
-		return;
-
 	/* Enable QSGMII AN */
 	/* Set page to 4 */
-	miiphy_write(name, devadr, 0x16, 4);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 4);
 	/* Enable AN */
-	miiphy_write(name, devadr, 0x0, 0x1140);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x0, 0x1140);
 	/* Set page to 0 */
-	miiphy_write(name, devadr, 0x16, 0);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 0);
 
 	/* Phy C_ANEG */
-	miiphy_read(name, devadr, 0x4, &reg);
+	reg = phy_read(phydev, MDIO_DEVAD_NONE, 0x4);
 	reg |= 0x1E0;
-	miiphy_write(name, devadr, 0x4, reg);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x4, reg);
 
 	/* Soft-Reset */
-	miiphy_write(name, devadr, 22, 0x0000);
-	miiphy_write(name, devadr, 0, 0x9140);
+	phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0000);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0, 0x9140);
 
 	/* Power up the phy */
-	miiphy_read(name, devadr, ETH_PHY_CTRL_REG, &reg);
+	reg = phy_read(phydev, MDIO_DEVAD_NONE, ETH_PHY_CTRL_REG);
 	reg &= ~(ETH_PHY_CTRL_POWER_DOWN_MASK);
-	miiphy_write(name, devadr, ETH_PHY_CTRL_REG, reg);
+	phy_write(phydev, MDIO_DEVAD_NONE, ETH_PHY_CTRL_REG, reg);
 
-	printf("88E1545 Initialized on %s\n", name);
+	printf("88E1545 Initialized\n");
+	return 0;
 }
-#endif /* CONFIG_RESET_PHY_R */
diff --git a/board/Marvell/db-mv784mp-gp/kwbimage.cfg b/board/Marvell/db-mv784mp-gp/kwbimage.cfg
index cc05792556..1f748db37c 100644
--- a/board/Marvell/db-mv784mp-gp/kwbimage.cfg
+++ b/board/Marvell/db-mv784mp-gp/kwbimage.cfg
@@ -9,4 +9,4 @@ VERSION		1
 BOOT_FROM	spi
 
 # Binary Header (bin_hdr) with DDR3 training code
-BINARY spl/u-boot-spl.bin 0000005b 00000068
+BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068