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| author | Kever Yang <kever.yang@rock-chips.com> | 2017-05-15 20:52:16 +0800 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2017-06-07 07:29:20 -0600 |
| commit | 1960b0103420a74ae5b154ed8684785036e2235b (patch) | |
| tree | 30f953ef8d11259b60f5603cdd4bd4ad4d2a9b71 /board/advantech | |
| parent | 37943aaeea55011d48a0a492838c50111ba2a37e (diff) | |
rockchip: clock: rk3036: some fix according TRM
- hclk/pclk_div range　should use '<=' instead of '<'
- use GPLL for pd_bus clock source
- pd_bus HCLK/PCLK clock rate should not bigger than ACLK
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'board/advantech')
0 files changed, 0 insertions, 0 deletions