diff options
| author | Marek Vasut <marex@denx.de> | 2015-08-10 21:37:14 +0200 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2015-08-23 11:56:20 +0200 |
| commit | c68eea0492e68e29ccdca5ac2b88c90899c4d80d (patch) | |
| tree | b64ad6409482d24c76e2bca8831f17ead37432a4 /board/altera/arria5-socdk/qts/sdram_config.h | |
| parent | f089240128329fe6a49a5272aef732b47613c2f5 (diff) | |
arm: socfpga: Remove CV-specific parts from AV-SoCDK
Just remove the CycloneV specific parts from the ArriaV SoCDK board
and they are no longer needed now.
Signed-off-by: Marek Vasut <marex@denx.de>
Diffstat (limited to 'board/altera/arria5-socdk/qts/sdram_config.h')
| -rw-r--r-- | board/altera/arria5-socdk/qts/sdram_config.h | 14 |
1 files changed, 0 insertions, 14 deletions
diff --git a/board/altera/arria5-socdk/qts/sdram_config.h b/board/altera/arria5-socdk/qts/sdram_config.h index f6d51ca8ef..2e26ae5bd8 100644 --- a/board/altera/arria5-socdk/qts/sdram_config.h +++ b/board/altera/arria5-socdk/qts/sdram_config.h @@ -20,7 +20,6 @@ #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7 -#ifdef CONFIG_SOCFPGA_ARRIA5 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 19 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 139 @@ -32,19 +31,6 @@ #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 19 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 26 -#else -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 14 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 -#endif /* CONFIG_SOCFPGA_ARRIA5 */ #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 |