diff options
| author | Kim Phillips <kim.phillips@freescale.com> | 2007-06-14 19:56:58 -0500 |
|---|---|---|
| committer | Kim Phillips <kim.phillips@freescale.com> | 2007-06-14 19:56:58 -0500 |
| commit | b721ff745d3e5b4fe6bb8db430553d54dba4bd17 (patch) | |
| tree | 8f267466c28352bac8e2f59358411d0860bb0bcf /board/amcc/acadia/memory.c | |
| parent | 5b1313fb2758ffce8b624457f777d8cc6709608d (diff) | |
| parent | 9912121f7ed804ea58fd62f3f230b5dcfc357d88 (diff) | |
Merge git://www.denx.de/git/u-boot
Diffstat (limited to 'board/amcc/acadia/memory.c')
| -rw-r--r-- | board/amcc/acadia/memory.c | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/board/amcc/acadia/memory.c b/board/amcc/acadia/memory.c index 5375d36c9b..25904d3b94 100644 --- a/board/amcc/acadia/memory.c +++ b/board/amcc/acadia/memory.c @@ -39,6 +39,7 @@ void sdram_init(void) return; } +#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) static void cram_bcr_write(u32 wr_val) { wr_val <<= 2; @@ -62,9 +63,12 @@ static void cram_bcr_write(u32 wr_val) return; } +#endif long int initdram(int board_type) { +#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) + int i; u32 val; /* 1. EBC need to program READY, CLK, ADV for ASync mode */ @@ -92,7 +96,12 @@ long int initdram(int board_type) /* Config EBC to use RDY */ mfsdr(sdrultra0, val); - mtsdr(sdrultra0, val | 0x04000000); + mtsdr(sdrultra0, val | SDR_ULTRA0_EBCRDYEN); + + /* Wait a short while, since for NAND booting this is too fast */ + for (i=0; i<200000; i++) + ; +#endif return (CFG_MBYTES_RAM << 20); } |