ppc4xx: Sequoia/Rainer: Check and reconfigure the PCI sync clock

This patch now uses the 440EP(x)/GR(x) function to check and dynamically
reconfigure the PCI sync clock.

Signed-off-by: Stefan Roese <sr@denx.de>

1 files changed, 23 insertions, 3 deletions

diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c
index d42c802538..00f6408720 100644
--- a/board/amcc/sequoia/sequoia.c
+++ b/board/amcc/sequoia/sequoia.c
@@ -40,6 +40,15 @@ extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH ch
 extern void __ft_board_setup(void *blob, bd_t *bd);
 ulong flash_get_size(ulong base, int banknum);
 
+static inline u32 get_async_pci_freq(void)
+{
+	if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) &
+		CONFIG_SYS_BCSR5_PCI66EN)
+		return 66666666;
+	else
+		return 33333333;
+}
+
 int board_early_init_f(void)
 {
 	u32 sdr0_cust0;
@@ -76,6 +85,9 @@ int board_early_init_f(void)
 	mtdcr(UIC2VR, 0x00000000);	/* int31 highest, base=0x000 */
 	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
 
+	/* Check and reconfigure the PCI sync clock if necessary */
+	ppc4xx_pci_sync_clock_config(get_async_pci_freq());
+
 	/* 50MHz tmrclk */
 	out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x04, 0x00);
 
@@ -319,7 +331,7 @@ int checkboard(void)
 {
 	char *s = getenv("serial#");
 	u8 rev;
-	u8 val;
+	u32 clock = get_async_pci_freq();
 
 #ifdef CONFIG_440EPX
 	printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board");
@@ -328,8 +340,7 @@ int checkboard(void)
 #endif
 
 	rev = in_8((void *)(CONFIG_SYS_BCSR_BASE + 0));
-	val = in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) & CONFIG_SYS_BCSR5_PCI66EN;
-	printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
+	printf(", Rev. %X, PCI-Async=%d MHz", rev, clock / 1000000);
 
 	if (s != NULL) {
 		puts(", serial# ");
@@ -337,6 +348,15 @@ int checkboard(void)
 	}
 	putc('\n');
 
+	/*
+	 * Reconfiguration of the PCI sync clock is already done,
+	 * now check again if everything is in range:
+	 */
+	if (ppc4xx_pci_sync_clock_config(clock)) {
+		printf("ERROR: PCI clocking incorrect (async=%d "
+		       "sync=%ld)!\n", clock, get_PCI_freq());
+	}
+
 	return (0);
 }