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authorZhichun Hua <zhichun.hua@freescale.com>2015-06-29 15:49:37 +0800
committerYork Sun <yorksun@freescale.com>2015-07-20 11:44:40 -0700
commit21a257b9b3b29ddb1445fdafe12e05727080a198 (patch)
tree87ea425ec314d57771e74a0200c5ad0684329541 /board/amcc/taishan/Makefile
parent25195600173e618b1cf693bcf38d48973e3a08fb (diff)
armv8: Fix TCR macros for shareability attribute
For ARMv8, outer shareable is 0b10, inner shareable is 0b11 at bit position [13:12] of TCR_ELx register. Signed-off-by: Zhichun Hua <zhichun.hua@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
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