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authorMarek Vasut <marex@denx.de>2017-11-09 11:50:13 +0100
committerStefano Babic <sbabic@denx.de>2017-11-16 10:43:22 +0100
commitb979e35230042bfeadd5f4eddf66232f29e4bff4 (patch)
tree5efda1c4b05b5273352f2d9ba8b201711241d880 /board/amlogic/odroid-c2
parentc253573f3e269fd9a24ee6684d87dd91106018a5 (diff)
ARM: imx6: Adjust DDR DRAM settings on DHCOM i.MX6 PDK
The board uses T-topology for the four x16 DRAM chips, so remove the write-leveling from the SPL as that is only usefly on fly-by topology and can be harmful on T-topology. Also update the DRAM timing with values from calibration on multiple boards. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
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