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authorTom Rini <trini@konsulko.com>2020-03-02 09:20:12 -0500
committerTom Rini <trini@konsulko.com>2020-03-02 09:20:12 -0500
commitbd7bb38699412bf95449bf9f23aa625c0436eae6 (patch)
tree4e30bec98504a3923d40df2594b48c173032e192 /board/avionic-design
parent5045289820835ce0baf5d7cea86f9fdc6170d189 (diff)
parent25974079750c5fbf920a226a26d8cb9b1aff2544 (diff)
Merge tag 'xilinx-for-v2020.04-rc4' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx fixes for v2020.04-rc4 - Fix link good bit handling in dp83867 - Rename generic Zynq defconfig - Fix zybo z7 low leve setup - Fix error path in zynq_gem driver and fix 64bit usage - Fix invalid clock name quieries for Versal - Fix zynq/zynqmp SPL low level configuration via DT selection
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