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| author | Milan Obuch <u-boot@dino.sk> | 2020-01-19 22:32:19 -0300 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2020-02-28 12:04:10 +0100 |
| commit | 1bf9e01b8f82c442029607ab953c6a0d099c7d68 (patch) | |
| tree | 41c6a8cdedd6813728a358223c3cbdcc1364e8be /board/bitmain/antminer_s9/Makefile | |
| parent | 1a4bf17b0298257b35611453e44f53c72a55f8a7 (diff) | |
arm: zynq: zybo z7: fix SPL uart init bitrate
The board uses 100 MHz clock for UART bitrate generator,
but is configured as 50 MHz on defconfig.
This produces wrong console output.
The first message, "Debug uart enabled" is received as:
"������b"
Fix the issue by configuring the correct clock for the
UART baudrate generator
Signed-off-by: Milan Obuch <u-boot@dino.sk>
Signed-off-by: Luis Araneda <luaraneda@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'board/bitmain/antminer_s9/Makefile')
0 files changed, 0 insertions, 0 deletions