diff options
| author | Tom Rini <trini@ti.com> | 2014-01-10 10:56:00 -0500 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2014-01-10 10:56:00 -0500 |
| commit | 7f673c99c2d8d1aa21996c5b914f06d784b080ca (patch) | |
| tree | df68108a0bd7326dc6299b96853b769220c55470 /board/compulab | |
| parent | 8401bfa91ef57e331e2a3abdf768d41803bec88e (diff) | |
| parent | 10a147bc665367111920be657409a5d56d3c0590 (diff) | |
Merge branch 'master' of git://git.denx.de/u-boot-arm
Bringing in the MMC tree means that CONFIG_BOUNCE_BUFFER needed to be
added to include/configs/exynos5-dt.h now.
Conflicts:
include/configs/exynos5250-dt.h
Signed-off-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'board/compulab')
| -rw-r--r-- | board/compulab/cm_t335/spl.c | 10 | ||||
| -rw-r--r-- | board/compulab/cm_t35/cm_t35.c | 18 |
2 files changed, 26 insertions, 2 deletions
diff --git a/board/compulab/cm_t335/spl.c b/board/compulab/cm_t335/spl.c index 99f3a869bb..b3b150a577 100644 --- a/board/compulab/cm_t335/spl.c +++ b/board/compulab/cm_t335/spl.c @@ -20,6 +20,14 @@ #include <asm/arch/hardware_am33xx.h> #include <asm/sizes.h> +const struct ctrl_ioregs ioregs = { + .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE, + .cm1ioctl = MT41J128MJT125_IOCTRL_VALUE, + .cm2ioctl = MT41J128MJT125_IOCTRL_VALUE, + .dt0ioctl = MT41J128MJT125_IOCTRL_VALUE, + .dt1ioctl = MT41J128MJT125_IOCTRL_VALUE, +}; + static const struct ddr_data ddr3_data = { .datardsratio0 = MT41J128MJT125_RD_DQS, .datawdsratio0 = MT41J128MJT125_WR_DQS, @@ -89,7 +97,7 @@ static void probe_sdram_size(long size) reset_cpu(0); } debug("%s: setting DRAM size to %ldM\n", __func__, size >> 20); - config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data, + config_ddr(303, &ioregs, &ddr3_data, &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); } diff --git a/board/compulab/cm_t35/cm_t35.c b/board/compulab/cm_t35/cm_t35.c index bc8e0cad94..00bcf41bb3 100644 --- a/board/compulab/cm_t35/cm_t35.c +++ b/board/compulab/cm_t35/cm_t35.c @@ -105,6 +105,22 @@ static inline int splash_load_from_nand(void) } #endif /* CONFIG_CMD_NAND */ +#ifdef CONFIG_SPL_BUILD +/* + * Routine: get_board_mem_timings + * Description: If we use SPL then there is no x-loader nor config header + * so we have to setup the DDR timings ourself on both banks. + */ +void get_board_mem_timings(struct board_sdrc_timings *timings) +{ + timings->mr = MICRON_V_MR_165; + timings->mcfg = MICRON_V_MCFG_200(256 << 20); /* raswidth 14 needed */ + timings->ctrla = MICRON_V_ACTIMA_165; + timings->ctrlb = MICRON_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; +} +#endif + int splash_screen_prepare(void) { char *env_splashimage_value; @@ -440,7 +456,7 @@ void set_muxconf_regs(void) cm_t3730_set_muxconf(); } -#ifdef CONFIG_GENERIC_MMC +#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_getcd(struct mmc *mmc) { u8 val; |