diff options
author | Tom Rix <Tom.Rix@windriver.com> | 2009-10-04 05:40:07 -0500 |
---|---|---|
committer | Tom Rix <Tom.Rix@windriver.com> | 2009-10-04 05:40:07 -0500 |
commit | 4d6c2dd7ed6c6bc4114ca5c7577560ea9ba50bd0 (patch) | |
tree | 676e49c06682ea211d2d909beb35cee5623d106e /board/csb272 | |
parent | 300d1137161a47573b0f6504f32371c8065b8d37 (diff) | |
parent | 1d96cfe8f5eebfc6ea39d1a387f35ca4499e6b67 (diff) |
Merge branch 'arm/master' into arm/next
Conflicts:
board/AtmarkTechno/suzaku/Makefile
board/amcc/acadia/acadia.c
board/amcc/katmai/katmai.c
board/amcc/luan/luan.c
board/amcc/ocotea/ocotea.c
board/cm-bf537u/Makefile
board/cray/L1/L1.c
board/csb272/csb272.c
board/csb472/csb472.c
board/eric/eric.c
board/eric/init.S
board/eukrea/cpuat91/Makefile
board/exbitgen/exbitgen.c
board/exbitgen/init.S
board/freescale/mpc8536ds/config.mk
board/g2000/g2000.c
board/jse/sdram.c
board/mpl/mip405/mip405.c
board/mpl/pip405/pip405.c
board/netstal/hcu5/hcu5.c
board/netstal/mcu25/mcu25.c
board/sc3/sc3.c
board/w7o/init.S
board/w7o/w7o.c
common/cmd_reginfo.c
cpu/ppc4xx/40x_spd_sdram.c
cpu/ppc4xx/44x_spd_ddr.c
doc/README.sbc8548
drivers/misc/fsl_law.c
fs/ubifs/ubifs.c
include/asm-ppc/immap_85xx.h
Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
Diffstat (limited to 'board/csb272')
-rw-r--r-- | board/csb272/csb272.c | 22 | ||||
-rw-r--r-- | board/csb272/init.S | 18 |
2 files changed, 20 insertions, 20 deletions
diff --git a/board/csb272/csb272.c b/board/csb272/csb272.c index cb24cd4ffe..d6d65cf45c 100644 --- a/board/csb272/csb272.c +++ b/board/csb272/csb272.c @@ -87,13 +87,13 @@ int board_early_init_f(void) | +-------------------------------------------------------------------------*/ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ - mtdcr (uicpr, 0xFFFFFF83); /* set int polarities */ - mtdcr (uictr, 0x10000000); /* set int trigger levels */ - mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0ER, 0x00000000); /* disable all ints */ + mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */ + mtdcr (UIC0PR, 0xFFFFFF83); /* set int polarities */ + mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ mtebc (EBC0_CFG, 0xa8400000); /* EBC always driven */ @@ -135,28 +135,28 @@ phys_size_t initdram (int board_type) tot_size = 0; - mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); tmp = mfdcr (SDRAM0_CFGDATA); if (tmp & 0x00000001) { bank_size = 0x00400000 << ((tmp >> 17) & 0x7); tot_size += bank_size; } - mtdcr (SDRAM0_CFGADDR, mem_mb1cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); tmp = mfdcr (SDRAM0_CFGDATA); if (tmp & 0x00000001) { bank_size = 0x00400000 << ((tmp >> 17) & 0x7); tot_size += bank_size; } - mtdcr (SDRAM0_CFGADDR, mem_mb2cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); tmp = mfdcr (SDRAM0_CFGDATA); if (tmp & 0x00000001) { bank_size = 0x00400000 << ((tmp >> 17) & 0x7); tot_size += bank_size; } - mtdcr (SDRAM0_CFGADDR, mem_mb3cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); tmp = mfdcr (SDRAM0_CFGDATA); if (tmp & 0x00000001) { bank_size = 0x00400000 << ((tmp >> 17) & 0x7); diff --git a/board/csb272/init.S b/board/csb272/init.S index 15b26f8bf8..a6b0d4045a 100644 --- a/board/csb272/init.S +++ b/board/csb272/init.S @@ -175,26 +175,26 @@ sdram_init: * Disable memory controller to allow * values to be changed. */ - WDCR_SDRAM(mem_mcopt1, 0x00000000) + WDCR_SDRAM(SDRAM0_CFG, 0x00000000) /* * Configure Memory Banks */ - WDCR_SDRAM(mem_mb0cf, 0x00084001) - WDCR_SDRAM(mem_mb1cf, 0x00000000) - WDCR_SDRAM(mem_mb2cf, 0x00000000) - WDCR_SDRAM(mem_mb3cf, 0x00000000) + WDCR_SDRAM(SDRAM0_B0CR, 0x00084001) + WDCR_SDRAM(SDRAM0_B1CR, 0x00000000) + WDCR_SDRAM(SDRAM0_B2CR, 0x00000000) + WDCR_SDRAM(SDRAM0_B3CR, 0x00000000) /* * Set up SDTR1 (SDRAM Timing Register) */ - WDCR_SDRAM(mem_sdtr1, 0x00854009) + WDCR_SDRAM(SDRAM0_TR, 0x00854009) /* * Set RTR (Refresh Timing Register) */ - WDCR_SDRAM(mem_rtr, 0x10000000) - /* WDCR_SDRAM(mem_rtr, 0x05f00000) */ + WDCR_SDRAM(SDRAM0_RTR, 0x10000000) + /* WDCR_SDRAM(SDRAM0_RTR, 0x05f00000) */ /******************************************************************** * Delay to ensure 200usec have elapsed since reset. Assume worst @@ -210,7 +210,7 @@ sdram_init: /******************************************************************** * Set memory controller options reg, MCOPT1. *******************************************************************/ - WDCR_SDRAM(mem_mcopt1,0x80800000) + WDCR_SDRAM(SDRAM0_CFG,0x80800000) ..sdri_done: blr /* Return to calling function */ |