diff options
| author | Marek Vasut <marex@denx.de> | 2015-09-08 19:51:05 +0200 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2015-09-12 20:25:00 +0200 |
| commit | 4ae6cfe33230592515f33c4a98cd3a5e22d44457 (patch) | |
| tree | d1fbf58a442bf113ab03ce15b63f70698be233bc /board/denx/mcvevk/qts/pll_config.h | |
| parent | 89983478bdc99996bbc26bd63fd00358d3082cbe (diff) | |
arm: socfpga: mcvevk: Update DRAM clock to 400MHz
The MCV SoM has DDR3-1600 DRAMs on it, update the DRAM speed
to 400MHz to make use of these DRAMs completely.
Signed-off-by: Marek Vasut <marex@denx.de>
Diffstat (limited to 'board/denx/mcvevk/qts/pll_config.h')
| -rw-r--r-- | board/denx/mcvevk/qts/pll_config.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/board/denx/mcvevk/qts/pll_config.h b/board/denx/mcvevk/qts/pll_config.h index aff4648d70..b718b39e96 100644 --- a/board/denx/mcvevk/qts/pll_config.h +++ b/board/denx/mcvevk/qts/pll_config.h @@ -45,8 +45,8 @@ #define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 #define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 -#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 2 -#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 79 +#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0 +#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31 #define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 #define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 #define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 @@ -63,7 +63,7 @@ #define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 #define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 #define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 -#define CONFIG_HPS_CLK_SDRVCO_HZ 666666666 +#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000 #define CONFIG_HPS_CLK_EMAC0_HZ 250000000 #define CONFIG_HPS_CLK_EMAC1_HZ 1953125 #define CONFIG_HPS_CLK_USBCLK_HZ 200000000 |