Merge branch 'master' of git://www.denx.de/git/u-boot-imx

10 files changed, 609 insertions, 1043 deletions

diff --git a/board/engicam/common/Makefile b/board/engicam/common/Makefile
new file mode 100644
index 0000000000..6630fea012
--- /dev/null
+++ b/board/engicam/common/Makefile
@@ -0,0 +1,7 @@
+# Copyright (C) 2016 Amarula Solutions B.V.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y := board.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
diff --git a/board/engicam/common/board.c b/board/engicam/common/board.c
new file mode 100644
index 0000000000..af4ef28dac
--- /dev/null
+++ b/board/engicam/common/board.c
@@ -0,0 +1,82 @@
+/*
+ * Copyright (C) 2016 Amarula Solutions B.V.
+ * Copyright (C) 2016 Engicam S.r.l.
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <mmc.h>
+#include <asm/arch/sys_proto.h>
+
+#include "board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+static void mmc_late_init(void)
+{
+	char cmd[32];
+	char mmcblk[32];
+	u32 dev_no = mmc_get_env_dev();
+
+	setenv_ulong("mmcdev", dev_no);
+
+	/* Set mmcblk env */
+	sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", dev_no);
+	setenv("mmcroot", mmcblk);
+
+	sprintf(cmd, "mmc dev %d", dev_no);
+	run_command(cmd, 0);
+}
+#endif
+
+int board_late_init(void)
+{
+	switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >>
+			IMX6_BMODE_SHIFT) {
+	case IMX6_BMODE_SD:
+	case IMX6_BMODE_ESD:
+	case IMX6_BMODE_MMC:
+	case IMX6_BMODE_EMMC:
+#ifdef CONFIG_ENV_IS_IN_MMC
+		mmc_late_init();
+#endif
+		setenv("modeboot", "mmcboot");
+		break;
+	case IMX6_BMODE_NAND:
+		setenv("modeboot", "nandboot");
+		break;
+	default:
+		setenv("modeboot", "");
+		break;
+	}
+
+	setenv_fdt_file();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_NAND_MXS
+	setup_gpmi_nand();
+#endif
+
+#ifdef CONFIG_VIDEO_IPUV3
+	setup_display();
+#endif
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+
+	return 0;
+}
diff --git a/board/engicam/common/board.h b/board/engicam/common/board.h
new file mode 100644
index 0000000000..f364a23296
--- /dev/null
+++ b/board/engicam/common/board.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (C) 2016 Amarula Solutions B.V.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+void setenv_fdt_file(void);
+void setup_gpmi_nand(void);
+void setup_display(void);
+#endif /* _BOARD_H_ */
diff --git a/board/engicam/common/spl.c b/board/engicam/common/spl.c
new file mode 100644
index 0000000000..ab0ab986bf
--- /dev/null
+++ b/board/engicam/common/spl.c
@@ -0,0 +1,393 @@
+/*
+ * Copyright (C) 2016 Amarula Solutions B.V.
+ * Copyright (C) 2016 Engicam S.r.l.
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <linux/sizes.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/video.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
+        PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
+        PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const uart_pads[] = {
+#ifdef CONFIG_MX6QDL
+        IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+        IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+#elif CONFIG_MX6UL
+	IOMUX_PADS(PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL)),
+	IOMUX_PADS(PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL)),
+#endif
+};
+
+#ifdef CONFIG_MX6QDL
+/*
+ * Driving strength:
+ *   0x30 == 40 Ohm
+ *   0x28 == 48 Ohm
+ */
+#define IMX6DQ_DRIVE_STRENGTH		0x30
+#define IMX6SDL_DRIVE_STRENGTH		0x28
+
+/* configure MX6Q/DUAL mmdc DDR io registers */
+static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
+	.dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_cas = IMX6DQ_DRIVE_STRENGTH,
+	.dram_ras = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_reset = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdba2 = 0x00000000,
+	.dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
+};
+
+/* configure MX6Q/DUAL mmdc GRP io registers */
+static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
+	.grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_addds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_ddrmode_ctl = 0x00020000,
+	.grp_ddrpke = 0x00000000,
+	.grp_ddrmode = 0x00020000,
+	.grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_ddr_type = 0x000c0000,
+};
+
+/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
+struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
+	.dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_cas = IMX6SDL_DRIVE_STRENGTH,
+	.dram_ras = IMX6SDL_DRIVE_STRENGTH,
+	.dram_reset = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdba2 = 0x00000000,
+	.dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
+};
+
+/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
+struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
+	.grp_ddr_type = 0x000c0000,
+	.grp_ddrmode_ctl = 0x00020000,
+	.grp_ddrpke = 0x00000000,
+	.grp_addds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_ddrmode = 0x00020000,
+	.grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
+};
+
+/* mt41j256 */
+static struct mx6_ddr3_cfg mt41j256 = {
+	.mem_speed = 1066,
+	.density = 2,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 13,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1375,
+	.trcmin = 4875,
+	.trasmin = 3500,
+	.SRT = 0,
+};
+
+static struct mx6_mmdc_calibration mx6dq_mmdc_calib = {
+	.p0_mpwldectrl0 = 0x000E0009,
+	.p0_mpwldectrl1 = 0x0018000E,
+	.p1_mpwldectrl0 = 0x00000007,
+	.p1_mpwldectrl1 = 0x00000000,
+	.p0_mpdgctrl0 = 0x43280334,
+	.p0_mpdgctrl1 = 0x031C0314,
+	.p1_mpdgctrl0 = 0x4318031C,
+	.p1_mpdgctrl1 = 0x030C0258,
+	.p0_mprddlctl = 0x3E343A40,
+	.p1_mprddlctl = 0x383C3844,
+	.p0_mpwrdlctl = 0x40404440,
+	.p1_mpwrdlctl = 0x4C3E4446,
+};
+
+/* DDR 64bit */
+static struct mx6_ddr_sysinfo mem_q = {
+	.ddr_type	= DDR_TYPE_DDR3,
+	.dsize		= 2,
+	.cs1_mirror	= 0,
+	/* config for full 4GB range so that get_mem_size() works */
+	.cs_density	= 32,
+	.ncs		= 1,
+	.bi_on		= 1,
+	.rtt_nom	= 2,
+	.rtt_wr		= 2,
+	.ralat		= 5,
+	.walat		= 0,
+	.mif3_mode	= 3,
+	.rst_to_cke	= 0x23,
+	.sde_to_rst	= 0x10,
+};
+
+static struct mx6_mmdc_calibration mx6dl_mmdc_calib = {
+	.p0_mpwldectrl0 = 0x001F0024,
+	.p0_mpwldectrl1 = 0x00110018,
+	.p1_mpwldectrl0 = 0x001F0024,
+	.p1_mpwldectrl1 = 0x00110018,
+	.p0_mpdgctrl0 = 0x4230022C,
+	.p0_mpdgctrl1 = 0x02180220,
+	.p1_mpdgctrl0 = 0x42440248,
+	.p1_mpdgctrl1 = 0x02300238,
+	.p0_mprddlctl = 0x44444A48,
+	.p1_mprddlctl = 0x46484A42,
+	.p0_mpwrdlctl = 0x38383234,
+	.p1_mpwrdlctl = 0x3C34362E,
+};
+
+/* DDR 64bit 1GB */
+static struct mx6_ddr_sysinfo mem_dl = {
+	.dsize		= 2,
+	.cs1_mirror	= 0,
+	/* config for full 4GB range so that get_mem_size() works */
+	.cs_density	= 32,
+	.ncs		= 1,
+	.bi_on		= 1,
+	.rtt_nom	= 1,
+	.rtt_wr		= 1,
+	.ralat		= 5,
+	.walat		= 0,
+	.mif3_mode	= 3,
+	.rst_to_cke	= 0x23,
+	.sde_to_rst	= 0x10,
+};
+
+/* DDR 32bit 512MB */
+static struct mx6_ddr_sysinfo mem_s = {
+	.dsize		= 1,
+	.cs1_mirror	= 0,
+	/* config for full 4GB range so that get_mem_size() works */
+	.cs_density	= 32,
+	.ncs		= 1,
+	.bi_on		= 1,
+	.rtt_nom	= 1,
+	.rtt_wr		= 1,
+	.ralat		= 5,
+	.walat		= 0,
+	.mif3_mode	= 3,
+	.rst_to_cke	= 0x23,
+	.sde_to_rst	= 0x10,
+};
+#endif /* CONFIG_MX6QDL */
+
+#ifdef CONFIG_MX6UL
+static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
+	.grp_addds = 0x00000030,
+	.grp_ddrmode_ctl = 0x00020000,
+	.grp_b0ds = 0x00000030,
+	.grp_ctlds = 0x00000030,
+	.grp_b1ds = 0x00000030,
+	.grp_ddrpke = 0x00000000,
+	.grp_ddrmode = 0x00020000,
+	.grp_ddr_type = 0x000c0000,
+};
+
+static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
+	.dram_dqm0 = 0x00000030,
+	.dram_dqm1 = 0x00000030,
+	.dram_ras = 0x00000030,
+	.dram_cas = 0x00000030,
+	.dram_odt0 = 0x00000030,
+	.dram_odt1 = 0x00000030,
+	.dram_sdba2 = 0x00000000,
+	.dram_sdclk_0 = 0x00000008,
+	.dram_sdqs0 = 0x00000038,
+	.dram_sdqs1 = 0x00000030,
+	.dram_reset = 0x00000030,
+};
+
+static struct mx6_mmdc_calibration mx6_mmcd_calib = {
+	.p0_mpwldectrl0 = 0x00070007,
+	.p0_mpdgctrl0 = 0x41490145,
+	.p0_mprddlctl = 0x40404546,
+	.p0_mpwrdlctl = 0x4040524D,
+};
+
+struct mx6_ddr_sysinfo ddr_sysinfo = {
+	.dsize = 0,
+	.cs_density = 20,
+	.ncs = 1,
+	.cs1_mirror = 0,
+	.rtt_wr = 2,
+	.rtt_nom = 1,		/* RTT_Nom = RZQ/2 */
+	.walat = 1,		/* Write additional latency */
+	.ralat = 5,		/* Read additional latency */
+	.mif3_mode = 3,		/* Command prediction working mode */
+	.bi_on = 1,		/* Bank interleaving enabled */
+	.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
+	.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
+	.ddr_type = DDR_TYPE_DDR3,
+};
+
+static struct mx6_ddr3_cfg mem_ddr = {
+	.mem_speed = 800,
+	.density = 4,
+	.width = 16,
+	.banks = 8,
+#ifdef TARGET_MX6UL_ISIOT
+	.rowaddr = 15,
+#else
+	.rowaddr = 13,
+#endif
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1375,
+	.trcmin = 4875,
+	.trasmin = 3500,
+};
+#endif /* CONFIG_MX6UL */
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+#ifdef CONFIG_MX6QDL
+	writel(0x00003F3F, &ccm->CCGR0);
+	writel(0x0030FC00, &ccm->CCGR1);
+	writel(0x000FC000, &ccm->CCGR2);
+	writel(0x3F300000, &ccm->CCGR3);
+	writel(0xFF00F300, &ccm->CCGR4);
+	writel(0x0F0000C3, &ccm->CCGR5);
+	writel(0x000003CC, &ccm->CCGR6);
+#elif CONFIG_MX6UL
+	writel(0x00c03f3f, &ccm->CCGR0);
+	writel(0xfcffff00, &ccm->CCGR1);
+	writel(0x0cffffcc, &ccm->CCGR2);
+	writel(0x3f3c3030, &ccm->CCGR3);
+	writel(0xff00fffc, &ccm->CCGR4);
+	writel(0x033f30ff, &ccm->CCGR5);
+	writel(0x00c00fff, &ccm->CCGR6);
+#endif
+}
+
+static void gpr_init(void)
+{
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	/* enable AXI cache for VDOA/VPU/IPU */
+	writel(0xF00000CF, &iomux->gpr[4]);
+	/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+	writel(0x007F007F, &iomux->gpr[6]);
+	writel(0x007F007F, &iomux->gpr[7]);
+}
+
+static void spl_dram_init(void)
+{
+#ifdef CONFIG_MX6QDL
+	if (is_mx6solo()) {
+		mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
+		mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256);
+	} else if (is_mx6dl()) {
+		mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
+		mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256);
+	} else if (is_mx6dq()) {
+		mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
+		mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256);
+	}
+#elif CONFIG_MX6UL
+	mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+	mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
+#endif
+
+	udelay(100);
+}
+
+void board_init_f(ulong dummy)
+{
+	ccgr_init();
+
+	/* setup AIPS and disable watchdog */
+	arch_cpu_init();
+
+	gpr_init();
+
+	/* iomux */
+	SETUP_IOMUX_PADS(uart_pads);
+
+	/* setup GP timer */
+	timer_init();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	/* load/boot image from boot device */
+	board_init_r(NULL, 0);
+}
diff --git a/board/engicam/geam6ul/geam6ul.c b/board/engicam/geam6ul/geam6ul.c
index 40f20a9bec..841ade98c5 100644
--- a/board/engicam/geam6ul/geam6ul.c
+++ b/board/engicam/geam6ul/geam6ul.c
@@ -7,6 +7,7 @@
  */
 
 #include <common.h>
+#include <mmc.h>
 
 #include <asm/io.h>
 #include <asm/gpio.h>
@@ -19,23 +20,9 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/imx-common/iomux-v3.h>
 
-DECLARE_GLOBAL_DATA_PTR;
-
-#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
-	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
-	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
-
-static iomux_v3_cfg_t const uart1_pads[] = {
-	MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-int board_early_init_f(void)
-{
-	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+#include "../common/board.h"
 
-	return 0;
-}
+DECLARE_GLOBAL_DATA_PTR;
 
 #ifdef CONFIG_NAND_MXS
 
@@ -45,29 +32,29 @@ int board_early_init_f(void)
 #define GPMI_PAD_CTRL2		(GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
 
 static iomux_v3_cfg_t const nand_pads[] = {
-	MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
-	MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
-	MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
-	MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
-	MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
-	MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
-	MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
-	MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
-	MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
-	MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
-	MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
-	MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
-	MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
-	MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
-	MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	IOMUX_PADS(PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
 };
 
-static void setup_gpmi_nand(void)
+void setup_gpmi_nand(void)
 {
 	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 
 	/* config gpmi nand iomux */
-	imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
+	SETUP_IOMUX_PADS(nand_pads);
 
 	clrbits_le32(&mxc_ccm->CCGR4,
 		     MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
@@ -103,32 +90,13 @@ static void setup_gpmi_nand(void)
 }
 #endif /* CONFIG_NAND_MXS */
 
-int board_init(void)
+void setenv_fdt_file(void)
 {
-	/* Address of boot parameters */
-	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-
-#ifdef CONFIG_NAND_MXS
-	setup_gpmi_nand();
-#endif
-
-	return 0;
-}
-
-int dram_init(void)
-{
-	gd->ram_size = imx_ddr_size();
-
-	return 0;
+	if (is_mx6ul())
+		setenv("fdt_file", "imx6ul-geam-kit.dtb");
 }
 
 #ifdef CONFIG_SPL_BUILD
-#include <libfdt.h>
-#include <spl.h>
-
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/mx6-ddr.h>
-
 /* MMC board initialization is needed till adding DM support in SPL */
 #if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
 #include <mmc.h>
@@ -139,19 +107,19 @@ int dram_init(void)
 	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
 static iomux_v3_cfg_t const usdhc1_pads[] = {
-	MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IOMUX_PADS(PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 
 	/* VSELECT */
-	MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IOMUX_PADS(PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 	/* CD */
-	MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	IOMUX_PADS(PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 	/* RST_B */
-	MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	IOMUX_PADS(PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 };
 
 #define USDHC1_CD_GPIO	IMX_GPIO_NR(1, 1)
@@ -186,8 +154,7 @@ int board_mmc_init(bd_t *bis)
 	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 		switch (i) {
 		case 0:
-			imx_iomux_v3_setup_multiple_pads(
-				usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+			SETUP_IOMUX_PADS(usdhc1_pads);
 			gpio_direction_input(USDHC1_CD_GPIO);
 			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 			break;
@@ -207,111 +174,4 @@ int board_mmc_init(bd_t *bis)
 	return 0;
 }
 #endif /* CONFIG_FSL_ESDHC */
-
-static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
-	.grp_addds = 0x00000030,
-	.grp_ddrmode_ctl = 0x00020000,
-	.grp_b0ds = 0x00000030,
-	.grp_ctlds = 0x00000030,
-	.grp_b1ds = 0x00000030,
-	.grp_ddrpke = 0x00000000,
-	.grp_ddrmode = 0x00020000,
-	.grp_ddr_type = 0x000c0000,
-};
-
-static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
-	.dram_dqm0 = 0x00000030,
-	.dram_dqm1 = 0x00000030,
-	.dram_ras = 0x00000030,
-	.dram_cas = 0x00000030,
-	.dram_odt0 = 0x00000030,
-	.dram_odt1 = 0x00000030,
-	.dram_sdba2 = 0x00000000,
-	.dram_sdclk_0 = 0x00000008,
-	.dram_sdqs0 = 0x00000038,
-	.dram_sdqs1 = 0x00000030,
-	.dram_reset = 0x00000030,
-};
-
-static struct mx6_mmdc_calibration mx6_mmcd_calib = {
-	.p0_mpwldectrl0 = 0x00070007,
-	.p0_mpdgctrl0 = 0x41490145,
-	.p0_mprddlctl = 0x40404546,
-	.p0_mpwrdlctl = 0x4040524D,
-};
-
-struct mx6_ddr_sysinfo ddr_sysinfo = {
-	.dsize = 0,
-	.cs_density = 20,
-	.ncs = 1,
-	.cs1_mirror = 0,
-	.rtt_wr = 2,
-	.rtt_nom = 1,		/* RTT_Nom = RZQ/2 */
-	.walat = 1,		/* Write additional latency */
-	.ralat = 5,		/* Read additional latency */
-	.mif3_mode = 3,		/* Command prediction working mode */
-	.bi_on = 1,		/* Bank interleaving enabled */
-	.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
-	.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
-	.ddr_type = DDR_TYPE_DDR3,
-};
-
-static struct mx6_ddr3_cfg mem_ddr = {
-	.mem_speed = 800,
-	.density = 4,
-	.width = 16,
-	.banks = 8,
-	.rowaddr = 13,
-	.coladdr = 10,
-	.pagesz = 2,
-	.trcd = 1375,
-	.trcmin = 4875,
-	.trasmin = 3500,
-};
-
-static void ccgr_init(void)
-{
-	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
-	writel(0xFFFFFFFF, &ccm->CCGR0);
-	writel(0xFFFFFFFF, &ccm->CCGR1);
-	writel(0xFFFFFFFF, &ccm->CCGR2);
-	writel(0xFFFFFFFF, &ccm->CCGR3);
-	writel(0xFFFFFFFF, &ccm->CCGR4);
-	writel(0xFFFFFFFF, &ccm->CCGR5);
-	writel(0xFFFFFFFF, &ccm->CCGR6);
-	writel(0xFFFFFFFF, &ccm->CCGR7);
-}
-
-static void spl_dram_init(void)
-{
-	mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
-	mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
-}
-
-void board_init_f(ulong dummy)
-{
-	/* setup AIPS and disable watchdog */
-	arch_cpu_init();
-
-	ccgr_init();
-
-	/* iomux and setup of i2c */
-	board_early_init_f();
-
-	/* setup GP timer */
-	timer_init();
-
-	/* UART clocks enabled and gd valid - init serial console */
-	preloader_console_init();
-
-	/* DDR initialization */
-	spl_dram_init();
-
-	/* Clear the BSS. */
-	memset(__bss_start, 0, __bss_end - __bss_start);
-
-	/* load/boot image from boot device */
-	board_init_r(NULL, 0);
-}
 #endif /* CONFIG_SPL_BUILD */
diff --git a/board/engicam/icorem6/MAINTAINERS b/board/engicam/icorem6/MAINTAINERS
index 6116648e37..26b4b56d71 100644
--- a/board/engicam/icorem6/MAINTAINERS
+++ b/board/engicam/icorem6/MAINTAINERS
@@ -3,10 +3,8 @@ M:	Jagan Teki <jagan@amarulasolutions.com>
 S:	Maintained
 F:	board/engicam/icorem6
 F:	include/configs/imx6qdl_icore.h
-F:	configs/imx6q_icore_mmc_defconfig
-F:	configs/imx6q_icore_nand_defconfig
-F:	configs/imx6dl_icore_mmc_defconfig
-F:	configs/imx6dl_icore_nand_defconfig
+F:	configs/imx6qdl_icore_mmc_defconfig
+F:	configs/imx6qdl_icore_nand_defconfig
 F:	arch/arm/dts/imx6qdl-icore.dtsi
 F:	arch/arm/dts/imx6q-icore.dts
 F:	arch/arm/dts/imx6dl-icore.dts
diff --git a/board/engicam/icorem6/icorem6.c b/board/engicam/icorem6/icorem6.c
index 171ec451a1..74cbbc5c56 100644
--- a/board/engicam/icorem6/icorem6.c
+++ b/board/engicam/icorem6/icorem6.c
@@ -7,6 +7,7 @@
  */
 
 #include <common.h>
+#include <mmc.h>
 
 #include <asm/io.h>
 #include <asm/gpio.h>
@@ -20,16 +21,9 @@
 #include <asm/imx-common/iomux-v3.h>
 #include <asm/imx-common/video.h>
 
-DECLARE_GLOBAL_DATA_PTR;
-
-#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
-	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
-	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+#include "../common/board.h"
 
-static iomux_v3_cfg_t const uart4_pads[] = {
-	IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
-	IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
-};
+DECLARE_GLOBAL_DATA_PTR;
 
 #ifdef CONFIG_NAND_MXS
 
@@ -56,7 +50,7 @@ iomux_v3_cfg_t gpmi_pads[] = {
 	IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
 };
 
-static void setup_gpmi_nand(void)
+void setup_gpmi_nand(void)
 {
 	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 
@@ -149,7 +143,7 @@ struct display_info_t const displays[] = {
 
 size_t display_count = ARRAY_SIZE(displays);
 
-static void setup_display(void)
+void setup_display(void)
 {
 	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
@@ -198,43 +192,15 @@ static void setup_display(void)
 }
 #endif /* CONFIG_VIDEO_IPUV3 */
 
-int board_early_init_f(void)
-{
-	SETUP_IOMUX_PADS(uart4_pads);
-
-	return 0;
-}
-
-int board_init(void)
+void setenv_fdt_file(void)
 {
-	/* Address of boot parameters */
-	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-
-#ifdef CONFIG_NAND_MXS
-	setup_gpmi_nand();
-#endif
-
-#ifdef CONFIG_VIDEO_IPUV3
-	setup_display();
-#endif
-
-	return 0;
-}
-
-int dram_init(void)
-{
-	gd->ram_size = imx_ddr_size();
-
-	return 0;
+	if (is_mx6dq())
+		setenv("fdt_file", "imx6q-icore.dtb");
+	else if(is_mx6dl() || is_mx6solo())
+		setenv("fdt_file", "imx6dl-icore.dtb");
 }
 
 #ifdef CONFIG_SPL_BUILD
-#include <libfdt.h>
-#include <spl.h>
-
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/mx6-ddr.h>
-
 /* MMC board initialization is needed till adding DM support in SPL */
 #if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
 #include <mmc.h>
@@ -307,273 +273,15 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
-/*
- * Driving strength:
- *   0x30 == 40 Ohm
- *   0x28 == 48 Ohm
- */
-
-#define IMX6DQ_DRIVE_STRENGTH		0x30
-#define IMX6SDL_DRIVE_STRENGTH		0x28
-
-/* configure MX6Q/DUAL mmdc DDR io registers */
-static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
-	.dram_sdqs0 = 0x28,
-	.dram_sdqs1 = 0x28,
-	.dram_sdqs2 = 0x28,
-	.dram_sdqs3 = 0x28,
-	.dram_sdqs4 = 0x28,
-	.dram_sdqs5 = 0x28,
-	.dram_sdqs6 = 0x28,
-	.dram_sdqs7 = 0x28,
-	.dram_dqm0 = 0x28,
-	.dram_dqm1 = 0x28,
-	.dram_dqm2 = 0x28,
-	.dram_dqm3 = 0x28,
-	.dram_dqm4 = 0x28,
-	.dram_dqm5 = 0x28,
-	.dram_dqm6 = 0x28,
-	.dram_dqm7 = 0x28,
-	.dram_cas = 0x30,
-	.dram_ras = 0x30,
-	.dram_sdclk_0 = 0x30,
-	.dram_sdclk_1 = 0x30,
-	.dram_reset = 0x30,
-	.dram_sdcke0 = 0x3000,
-	.dram_sdcke1 = 0x3000,
-	.dram_sdba2 = 0x00000000,
-	.dram_sdodt0 = 0x30,
-	.dram_sdodt1 = 0x30,
-};
-
-/* configure MX6Q/DUAL mmdc GRP io registers */
-static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
-	.grp_b0ds = 0x30,
-	.grp_b1ds = 0x30,
-	.grp_b2ds = 0x30,
-	.grp_b3ds = 0x30,
-	.grp_b4ds = 0x30,
-	.grp_b5ds = 0x30,
-	.grp_b6ds = 0x30,
-	.grp_b7ds = 0x30,
-	.grp_addds = 0x30,
-	.grp_ddrmode_ctl = 0x00020000,
-	.grp_ddrpke = 0x00000000,
-	.grp_ddrmode = 0x00020000,
-	.grp_ctlds = 0x30,
-	.grp_ddr_type = 0x000c0000,
-};
-
-/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
-struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
-	.dram_sdclk_0 = 0x30,
-	.dram_sdclk_1 = 0x30,
-	.dram_cas = 0x30,
-	.dram_ras = 0x30,
-	.dram_reset = 0x30,
-	.dram_sdcke0 = 0x30,
-	.dram_sdcke1 = 0x30,
-	.dram_sdba2 = 0x00000000,
-	.dram_sdodt0 = 0x30,
-	.dram_sdodt1 = 0x30,
-	.dram_sdqs0 = 0x28,
-	.dram_sdqs1 = 0x28,
-	.dram_sdqs2 = 0x28,
-	.dram_sdqs3 = 0x28,
-	.dram_sdqs4 = 0x28,
-	.dram_sdqs5 = 0x28,
-	.dram_sdqs6 = 0x28,
-	.dram_sdqs7 = 0x28,
-	.dram_dqm0 = 0x28,
-	.dram_dqm1 = 0x28,
-	.dram_dqm2 = 0x28,
-	.dram_dqm3 = 0x28,
-	.dram_dqm4 = 0x28,
-	.dram_dqm5 = 0x28,
-	.dram_dqm6 = 0x28,
-	.dram_dqm7 = 0x28,
-};
-
-/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
-struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
-	.grp_ddr_type = 0x000c0000,
-	.grp_ddrmode_ctl = 0x00020000,
-	.grp_ddrpke = 0x00000000,
-	.grp_addds = 0x30,
-	.grp_ctlds = 0x30,
-	.grp_ddrmode = 0x00020000,
-	.grp_b0ds = 0x28,
-	.grp_b1ds = 0x28,
-	.grp_b2ds = 0x28,
-	.grp_b3ds = 0x28,
-	.grp_b4ds = 0x28,
-	.grp_b5ds = 0x28,
-	.grp_b6ds = 0x28,
-	.grp_b7ds = 0x28,
-};
-
-/* mt41j256 */
-static struct mx6_ddr3_cfg mt41j256 = {
-	.mem_speed = 1066,
-	.density = 2,
-	.width = 16,
-	.banks = 8,
-	.rowaddr = 13,
-	.coladdr = 10,
-	.pagesz = 2,
-	.trcd = 1375,
-	.trcmin = 4875,
-	.trasmin = 3500,
-	.SRT = 0,
-};
-
-static struct mx6_mmdc_calibration mx6dq_mmdc_calib = {
-	.p0_mpwldectrl0 = 0x000E0009,
-	.p0_mpwldectrl1 = 0x0018000E,
-	.p1_mpwldectrl0 = 0x00000007,
-	.p1_mpwldectrl1 = 0x00000000,
-	.p0_mpdgctrl0 = 0x43280334,
-	.p0_mpdgctrl1 = 0x031C0314,
-	.p1_mpdgctrl0 = 0x4318031C,
-	.p1_mpdgctrl1 = 0x030C0258,
-	.p0_mprddlctl = 0x3E343A40,
-	.p1_mprddlctl = 0x383C3844,
-	.p0_mpwrdlctl = 0x40404440,
-	.p1_mpwrdlctl = 0x4C3E4446,
-};
-
-/* DDR 64bit */
-static struct mx6_ddr_sysinfo mem_q = {
-	.ddr_type	= DDR_TYPE_DDR3,
-	.dsize		= 2,
-	.cs1_mirror	= 0,
-	/* config for full 4GB range so that get_mem_size() works */
-	.cs_density	= 32,
-	.ncs		= 1,
-	.bi_on		= 1,
-	.rtt_nom	= 2,
-	.rtt_wr		= 2,
-	.ralat		= 5,
-	.walat		= 0,
-	.mif3_mode	= 3,
-	.rst_to_cke	= 0x23,
-	.sde_to_rst	= 0x10,
-};
-
-static struct mx6_mmdc_calibration mx6dl_mmdc_calib = {
-	.p0_mpwldectrl0 = 0x001F0024,
-	.p0_mpwldectrl1 = 0x00110018,
-	.p1_mpwldectrl0 = 0x001F0024,
-	.p1_mpwldectrl1 = 0x00110018,
-	.p0_mpdgctrl0 = 0x4230022C,
-	.p0_mpdgctrl1 = 0x02180220,
-	.p1_mpdgctrl0 = 0x42440248,
-	.p1_mpdgctrl1 = 0x02300238,
-	.p0_mprddlctl = 0x44444A48,
-	.p1_mprddlctl = 0x46484A42,
-	.p0_mpwrdlctl = 0x38383234,
-	.p1_mpwrdlctl = 0x3C34362E,
-};
-
-/* DDR 64bit 1GB */
-static struct mx6_ddr_sysinfo mem_dl = {
-	.dsize		= 2,
-	.cs1_mirror	= 0,
-	/* config for full 4GB range so that get_mem_size() works */
-	.cs_density	= 32,
-	.ncs		= 1,
-	.bi_on		= 1,
-	.rtt_nom	= 1,
-	.rtt_wr		= 1,
-	.ralat		= 5,
-	.walat		= 0,
-	.mif3_mode	= 3,
-	.rst_to_cke	= 0x23,
-	.sde_to_rst	= 0x10,
-};
-
-/* DDR 32bit 512MB */
-static struct mx6_ddr_sysinfo mem_s = {
-	.dsize		= 1,
-	.cs1_mirror	= 0,
-	/* config for full 4GB range so that get_mem_size() works */
-	.cs_density	= 32,
-	.ncs		= 1,
-	.bi_on		= 1,
-	.rtt_nom	= 1,
-	.rtt_wr		= 1,
-	.ralat		= 5,
-	.walat		= 0,
-	.mif3_mode	= 3,
-	.rst_to_cke	= 0x23,
-	.sde_to_rst	= 0x10,
-};
-
-static void ccgr_init(void)
-{
-	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
-	writel(0x00003F3F, &ccm->CCGR0);
-	writel(0x0030FC00, &ccm->CCGR1);
-	writel(0x000FC000, &ccm->CCGR2);
-	writel(0x3F300000, &ccm->CCGR3);
-	writel(0xFF00F300, &ccm->CCGR4);
-	writel(0x0F0000C3, &ccm->CCGR5);
-	writel(0x000003CC, &ccm->CCGR6);
-}
-
-static void gpr_init(void)
-{
-	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
-
-	/* enable AXI cache for VDOA/VPU/IPU */
-	writel(0xF00000CF, &iomux->gpr[4]);
-	/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-	writel(0x007F007F, &iomux->gpr[6]);
-	writel(0x007F007F, &iomux->gpr[7]);
-}
-
-static void spl_dram_init(void)
-{
-	if (is_mx6solo()) {
-		mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
-		mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256);
-	} else if (is_mx6dl()) {
-		mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
-		mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256);
-	} else if (is_mx6dq()) {
-		mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
-		mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256);
-	}
-
-	udelay(100);
-}
-
-void board_init_f(ulong dummy)
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
 {
-	ccgr_init();
-
-	/* setup AIPS and disable watchdog */
-	arch_cpu_init();
-
-	gpr_init();
-
-	/* iomux */
-	board_early_init_f();
-
-	/* setup GP timer */
-	timer_init();
-
-	/* UART clocks enabled and gd valid - init serial console */
-	preloader_console_init();
-
-	/* DDR initialization */
-	spl_dram_init();
-
-	/* Clear the BSS. */
-	memset(__bss_start, 0, __bss_end - __bss_start);
-
-	/* load/boot image from boot device */
-	board_init_r(NULL, 0);
+	if (is_mx6dq() && !strcmp(name, "imx6q-icore"))
+		return 0;
+	else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore"))
+		return 0;
+	else
+		return -1;
 }
 #endif
+#endif /* CONFIG_SPL_BUILD */
diff --git a/board/engicam/icorem6_rqs/MAINTAINERS b/board/engicam/icorem6_rqs/MAINTAINERS
index 2d2295c3c5..74470ba59f 100644
--- a/board/engicam/icorem6_rqs/MAINTAINERS
+++ b/board/engicam/icorem6_rqs/MAINTAINERS
@@ -3,8 +3,7 @@ M:	Jagan Teki <jagan@amarulasolutions.com>
 S:	Maintained
 F:	board/engicam/icorem6_rqs
 F:	include/configs/imx6qdl_icore_rqs.h
-F:	configs/imx6q_icore_rqs_mmc_defconfig
-F:	configs/imx6dl_icore_rqs_mmc_defconfig
+F:	configs/imx6qdl_icore_rqs_mmc_defconfig
 F:	arch/arm/dts/imx6qdl-icore-rqs.dtsi
 F:	arch/arm/dts/imx6q-icore-rqs.dts
 F:	arch/arm/dts/imx6dl-icore-rqs.dts
diff --git a/board/engicam/icorem6_rqs/icorem6_rqs.c b/board/engicam/icorem6_rqs/icorem6_rqs.c
index 01380f1269..c3c3173f51 100644
--- a/board/engicam/icorem6_rqs/icorem6_rqs.c
+++ b/board/engicam/icorem6_rqs/icorem6_rqs.c
@@ -20,31 +20,9 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/imx-common/iomux-v3.h>
 
-DECLARE_GLOBAL_DATA_PTR;
-
-#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
-	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
-	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
-
-static iomux_v3_cfg_t const uart4_pads[] = {
-	IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
-	IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
-};
-
-int board_early_init_f(void)
-{
-	SETUP_IOMUX_PADS(uart4_pads);
-
-	return 0;
-}
-
-int board_init(void)
-{
-	/* Address of boot parameters */
-	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+#include "../common/board.h"
 
-	return 0;
-}
+DECLARE_GLOBAL_DATA_PTR;
 
 #ifdef CONFIG_ENV_IS_IN_MMC
 int board_mmc_get_env_dev(int devno)
@@ -52,59 +30,19 @@ int board_mmc_get_env_dev(int devno)
 	/* dev 0 for SD/eSD, dev 1 for MMC/eMMC */
 	return (devno == 3) ? 1 : 0;
 }
-
-static void mmc_late_init(void)
-{
-	char cmd[32];
-	char mmcblk[32];
-	u32 dev_no = mmc_get_env_dev();
-
-	setenv_ulong("mmcdev", dev_no);
-
-	/* Set mmcblk env */
-	sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", dev_no);
-	setenv("mmcroot", mmcblk);
-
-	sprintf(cmd, "mmc dev %d", dev_no);
-	run_command(cmd, 0);
-}
 #endif
 
-int board_late_init(void)
+void setenv_fdt_file(void)
 {
-	switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >>
-			IMX6_BMODE_SHIFT) {
-	case IMX6_BMODE_SD:
-	case IMX6_BMODE_ESD:
-	case IMX6_BMODE_MMC:
-	case IMX6_BMODE_EMMC:
-#ifdef CONFIG_ENV_IS_IN_MMC
-		mmc_late_init();
-#endif
-		setenv("modeboot", "mmcboot");
-		break;
-	default:
-		setenv("modeboot", "");
-		break;
-	}
-
-	return 0;
-}
-
-int dram_init(void)
-{
-	gd->ram_size = imx_ddr_size();
-
-	return 0;
+	if (is_mx6dq())
+		setenv("fdt_file", "imx6q-icore-rqs.dtb");
+	else if(is_mx6dl() || is_mx6solo())
+		setenv("fdt_file", "imx6dl-icore-rqs.dtb");
 }
 
 #ifdef CONFIG_SPL_BUILD
-#include <libfdt.h>
 #include <spl.h>
 
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/mx6-ddr.h>
-
 /* MMC board initialization is needed till adding DM support in SPL */
 #if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
 #include <mmc.h>
@@ -219,273 +157,15 @@ void board_boot_order(u32 *spl_boot_list)
 #endif
 #endif
 
-/*
- * Driving strength:
- *   0x30 == 40 Ohm
- *   0x28 == 48 Ohm
- */
-
-#define IMX6DQ_DRIVE_STRENGTH		0x30
-#define IMX6SDL_DRIVE_STRENGTH		0x28
-
-/* configure MX6Q/DUAL mmdc DDR io registers */
-static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
-	.dram_sdqs0 = 0x28,
-	.dram_sdqs1 = 0x28,
-	.dram_sdqs2 = 0x28,
-	.dram_sdqs3 = 0x28,
-	.dram_sdqs4 = 0x28,
-	.dram_sdqs5 = 0x28,
-	.dram_sdqs6 = 0x28,
-	.dram_sdqs7 = 0x28,
-	.dram_dqm0 = 0x28,
-	.dram_dqm1 = 0x28,
-	.dram_dqm2 = 0x28,
-	.dram_dqm3 = 0x28,
-	.dram_dqm4 = 0x28,
-	.dram_dqm5 = 0x28,
-	.dram_dqm6 = 0x28,
-	.dram_dqm7 = 0x28,
-	.dram_cas = 0x30,
-	.dram_ras = 0x30,
-	.dram_sdclk_0 = 0x30,
-	.dram_sdclk_1 = 0x30,
-	.dram_reset = 0x30,
-	.dram_sdcke0 = 0x3000,
-	.dram_sdcke1 = 0x3000,
-	.dram_sdba2 = 0x00000000,
-	.dram_sdodt0 = 0x30,
-	.dram_sdodt1 = 0x30,
-};
-
-/* configure MX6Q/DUAL mmdc GRP io registers */
-static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
-	.grp_b0ds = 0x30,
-	.grp_b1ds = 0x30,
-	.grp_b2ds = 0x30,
-	.grp_b3ds = 0x30,
-	.grp_b4ds = 0x30,
-	.grp_b5ds = 0x30,
-	.grp_b6ds = 0x30,
-	.grp_b7ds = 0x30,
-	.grp_addds = 0x30,
-	.grp_ddrmode_ctl = 0x00020000,
-	.grp_ddrpke = 0x00000000,
-	.grp_ddrmode = 0x00020000,
-	.grp_ctlds = 0x30,
-	.grp_ddr_type = 0x000c0000,
-};
-
-/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
-struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
-	.dram_sdclk_0 = 0x30,
-	.dram_sdclk_1 = 0x30,
-	.dram_cas = 0x30,
-	.dram_ras = 0x30,
-	.dram_reset = 0x30,
-	.dram_sdcke0 = 0x30,
-	.dram_sdcke1 = 0x30,
-	.dram_sdba2 = 0x00000000,
-	.dram_sdodt0 = 0x30,
-	.dram_sdodt1 = 0x30,
-	.dram_sdqs0 = 0x28,
-	.dram_sdqs1 = 0x28,
-	.dram_sdqs2 = 0x28,
-	.dram_sdqs3 = 0x28,
-	.dram_sdqs4 = 0x28,
-	.dram_sdqs5 = 0x28,
-	.dram_sdqs6 = 0x28,
-	.dram_sdqs7 = 0x28,
-	.dram_dqm0 = 0x28,
-	.dram_dqm1 = 0x28,
-	.dram_dqm2 = 0x28,
-	.dram_dqm3 = 0x28,
-	.dram_dqm4 = 0x28,
-	.dram_dqm5 = 0x28,
-	.dram_dqm6 = 0x28,
-	.dram_dqm7 = 0x28,
-};
-
-/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
-struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
-	.grp_ddr_type = 0x000c0000,
-	.grp_ddrmode_ctl = 0x00020000,
-	.grp_ddrpke = 0x00000000,
-	.grp_addds = 0x30,
-	.grp_ctlds = 0x30,
-	.grp_ddrmode = 0x00020000,
-	.grp_b0ds = 0x28,
-	.grp_b1ds = 0x28,
-	.grp_b2ds = 0x28,
-	.grp_b3ds = 0x28,
-	.grp_b4ds = 0x28,
-	.grp_b5ds = 0x28,
-	.grp_b6ds = 0x28,
-	.grp_b7ds = 0x28,
-};
-
-/* mt41j256 */
-static struct mx6_ddr3_cfg mt41j256 = {
-	.mem_speed = 1066,
-	.density = 2,
-	.width = 16,
-	.banks = 8,
-	.rowaddr = 13,
-	.coladdr = 10,
-	.pagesz = 2,
-	.trcd = 1375,
-	.trcmin = 4875,
-	.trasmin = 3500,
-	.SRT = 0,
-};
-
-static struct mx6_mmdc_calibration mx6dq_mmdc_calib = {
-	.p0_mpwldectrl0 = 0x000E0009,
-	.p0_mpwldectrl1 = 0x0018000E,
-	.p1_mpwldectrl0 = 0x00000007,
-	.p1_mpwldectrl1 = 0x00000000,
-	.p0_mpdgctrl0 = 0x43280334,
-	.p0_mpdgctrl1 = 0x031C0314,
-	.p1_mpdgctrl0 = 0x4318031C,
-	.p1_mpdgctrl1 = 0x030C0258,
-	.p0_mprddlctl = 0x3E343A40,
-	.p1_mprddlctl = 0x383C3844,
-	.p0_mpwrdlctl = 0x40404440,
-	.p1_mpwrdlctl = 0x4C3E4446,
-};
-
-/* DDR 64bit */
-static struct mx6_ddr_sysinfo mem_q = {
-	.ddr_type	= DDR_TYPE_DDR3,
-	.dsize		= 2,
-	.cs1_mirror	= 0,
-	/* config for full 4GB range so that get_mem_size() works */
-	.cs_density	= 32,
-	.ncs		= 1,
-	.bi_on		= 1,
-	.rtt_nom	= 2,
-	.rtt_wr		= 2,
-	.ralat		= 5,
-	.walat		= 0,
-	.mif3_mode	= 3,
-	.rst_to_cke	= 0x23,
-	.sde_to_rst	= 0x10,
-};
-
-static struct mx6_mmdc_calibration mx6dl_mmdc_calib = {
-	.p0_mpwldectrl0 = 0x001F0024,
-	.p0_mpwldectrl1 = 0x00110018,
-	.p1_mpwldectrl0 = 0x001F0024,
-	.p1_mpwldectrl1 = 0x00110018,
-	.p0_mpdgctrl0 = 0x4230022C,
-	.p0_mpdgctrl1 = 0x02180220,
-	.p1_mpdgctrl0 = 0x42440248,
-	.p1_mpdgctrl1 = 0x02300238,
-	.p0_mprddlctl = 0x44444A48,
-	.p1_mprddlctl = 0x46484A42,
-	.p0_mpwrdlctl = 0x38383234,
-	.p1_mpwrdlctl = 0x3C34362E,
-};
-
-/* DDR 64bit 1GB */
-static struct mx6_ddr_sysinfo mem_dl = {
-	.dsize		= 2,
-	.cs1_mirror	= 0,
-	/* config for full 4GB range so that get_mem_size() works */
-	.cs_density	= 32,
-	.ncs		= 1,
-	.bi_on		= 1,
-	.rtt_nom	= 1,
-	.rtt_wr		= 1,
-	.ralat		= 5,
-	.walat		= 0,
-	.mif3_mode	= 3,
-	.rst_to_cke	= 0x23,
-	.sde_to_rst	= 0x10,
-};
-
-/* DDR 32bit 512MB */
-static struct mx6_ddr_sysinfo mem_s = {
-	.dsize		= 1,
-	.cs1_mirror	= 0,
-	/* config for full 4GB range so that get_mem_size() works */
-	.cs_density	= 32,
-	.ncs		= 1,
-	.bi_on		= 1,
-	.rtt_nom	= 1,
-	.rtt_wr		= 1,
-	.ralat		= 5,
-	.walat		= 0,
-	.mif3_mode	= 3,
-	.rst_to_cke	= 0x23,
-	.sde_to_rst	= 0x10,
-};
-
-static void ccgr_init(void)
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
 {
-	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
-	writel(0x00003F3F, &ccm->CCGR0);
-	writel(0x0030FC00, &ccm->CCGR1);
-	writel(0x000FC000, &ccm->CCGR2);
-	writel(0x3F300000, &ccm->CCGR3);
-	writel(0xFF00F300, &ccm->CCGR4);
-	writel(0x0F0000C3, &ccm->CCGR5);
-	writel(0x000003CC, &ccm->CCGR6);
-}
-
-static void gpr_init(void)
-{
-	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
-
-	/* enable AXI cache for VDOA/VPU/IPU */
-	writel(0xF00000CF, &iomux->gpr[4]);
-	/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-	writel(0x007F007F, &iomux->gpr[6]);
-	writel(0x007F007F, &iomux->gpr[7]);
-}
-
-static void spl_dram_init(void)
-{
-	if (is_mx6solo()) {
-		mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
-		mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256);
-	} else if (is_mx6dl()) {
-		mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
-		mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256);
-	} else if (is_mx6dq()) {
-		mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
-		mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256);
-	}
-
-	udelay(100);
-}
-
-void board_init_f(ulong dummy)
-{
-	ccgr_init();
-
-	/* setup AIPS and disable watchdog */
-	arch_cpu_init();
-
-	gpr_init();
-
-	/* iomux */
-	board_early_init_f();
-
-	/* setup GP timer */
-	timer_init();
-
-	/* UART clocks enabled and gd valid - init serial console */
-	preloader_console_init();
-
-	/* DDR initialization */
-	spl_dram_init();
-
-	/* Clear the BSS. */
-	memset(__bss_start, 0, __bss_end - __bss_start);
-
-	/* load/boot image from boot device */
-	board_init_r(NULL, 0);
+	if (is_mx6dq() && !strcmp(name, "imx6q-icore-rqs"))
+		return 0;
+	else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore-rqs"))
+		return 0;
+	else
+		return -1;
 }
 #endif
+#endif /* CONFIG_SPL_BUILD */
diff --git a/board/engicam/isiotmx6ul/isiotmx6ul.c b/board/engicam/isiotmx6ul/isiotmx6ul.c
index 29a137dc81..105db73f6d 100644
--- a/board/engicam/isiotmx6ul/isiotmx6ul.c
+++ b/board/engicam/isiotmx6ul/isiotmx6ul.c
@@ -20,23 +20,9 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/imx-common/iomux-v3.h>
 
-DECLARE_GLOBAL_DATA_PTR;
-
-#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE | \
-			PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
-			PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+#include "../common/board.h"
 
-static iomux_v3_cfg_t const uart1_pads[] = {
-	MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-int board_early_init_f(void)
-{
-	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
-
-	return 0;
-}
+DECLARE_GLOBAL_DATA_PTR;
 
 #ifdef CONFIG_NAND_MXS
 
@@ -46,29 +32,29 @@ int board_early_init_f(void)
 #define GPMI_PAD_CTRL2		(GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
 
 static iomux_v3_cfg_t const nand_pads[] = {
-	MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
-	MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
-	MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
-	MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
-	MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
-	MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
-	MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
-	MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
-	MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
-	MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
-	MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
-	MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
-	MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
-	MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
-	MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	IOMUX_PADS(PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
 };
 
-static void setup_gpmi_nand(void)
+void setup_gpmi_nand(void)
 {
 	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 
 	/* config gpmi nand iomux */
-	imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
+	SETUP_IOMUX_PADS(nand_pads);
 
 	clrbits_le32(&mxc_ccm->CCGR4,
 		     MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
@@ -110,73 +96,22 @@ int board_mmc_get_env_dev(int devno)
 	/* dev 0 for SD/eSD, dev 1 for MMC/eMMC */
 	return (devno == 0) ? 0 : 1;
 }
-
-static void mmc_late_init(void)
-{
-	char cmd[32];
-	char mmcblk[32];
-	u32 dev_no = mmc_get_env_dev();
-
-	setenv_ulong("mmcdev", dev_no);
-
-	/* Set mmcblk env */
-	sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", dev_no);
-	setenv("mmcroot", mmcblk);
-
-	sprintf(cmd, "mmc dev %d", dev_no);
-	run_command(cmd, 0);
-}
 #endif
 
-int board_late_init(void)
+void setenv_fdt_file(void)
 {
-	switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >>
-			IMX6_BMODE_SHIFT) {
-	case IMX6_BMODE_SD:
-	case IMX6_BMODE_ESD:
-	case IMX6_BMODE_MMC:
-	case IMX6_BMODE_EMMC:
+	if (is_mx6ul()) {
 #ifdef CONFIG_ENV_IS_IN_MMC
-		mmc_late_init();
+		setenv("fdt_file", "imx6ul-isiot-emmc.dtb");
+#else
+		setenv("fdt_file", "imx6ul-isiot-nand.dtb");
 #endif
-		setenv("modeboot", "mmcboot");
-		break;
-	case IMX6_BMODE_NAND:
-		setenv("modeboot", "nandboot");
-		break;
-	default:
-		setenv("modeboot", "");
-		break;
 	}
-
-	return 0;
-}
-
-int board_init(void)
-{
-	/* Address of boot parameters */
-	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-
-#ifdef CONFIG_NAND_MXS
-	setup_gpmi_nand();
-#endif
-	return 0;
-}
-
-int dram_init(void)
-{
-	gd->ram_size = imx_ddr_size();
-
-	return 0;
 }
 
 #ifdef CONFIG_SPL_BUILD
-#include <libfdt.h>
 #include <spl.h>
 
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/mx6-ddr.h>
-
 /* MMC board initialization is needed till adding DM support in SPL */
 #if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
 #include <mmc.h>
@@ -187,31 +122,31 @@ int dram_init(void)
 	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
 static iomux_v3_cfg_t const usdhc1_pads[] = {
-	MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IOMUX_PADS(PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 
 	/* VSELECT */
-	MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IOMUX_PADS(PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 	/* CD */
-	MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	IOMUX_PADS(PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 	/* RST_B */
-	MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	IOMUX_PADS(PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 };
 
 static iomux_v3_cfg_t const usdhc2_pads[] = {
-	MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IOMUX_PADS(PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 };
 
 #define USDHC1_CD_GPIO	IMX_GPIO_NR(1, 19)
@@ -252,14 +187,12 @@ int board_mmc_init(bd_t *bis)
 	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 		switch (i) {
 		case 0:
-			imx_iomux_v3_setup_multiple_pads(
-				usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+			SETUP_IOMUX_PADS(usdhc1_pads);
 			gpio_direction_input(USDHC1_CD_GPIO);
 			usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 			break;
 		case 1:
-			imx_iomux_v3_setup_multiple_pads(
-				usdhc1_pads, ARRAY_SIZE(usdhc2_pads));
+			SETUP_IOMUX_PADS(usdhc2_pads);
 			gpio_direction_input(USDHC2_CD_GPIO);
 			usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 			break;
@@ -305,110 +238,4 @@ void board_boot_order(u32 *spl_boot_list)
 }
 #endif
 #endif /* CONFIG_FSL_ESDHC */
-
-static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
-	.grp_addds = 0x00000030,
-	.grp_ddrmode_ctl = 0x00020000,
-	.grp_b0ds = 0x00000030,
-	.grp_ctlds = 0x00000030,
-	.grp_b1ds = 0x00000030,
-	.grp_ddrpke = 0x00000000,
-	.grp_ddrmode = 0x00020000,
-	.grp_ddr_type = 0x000c0000,
-};
-
-static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
-	.dram_dqm0 = 0x00000030,
-	.dram_dqm1 = 0x00000030,
-	.dram_ras = 0x00000030,
-	.dram_cas = 0x00000030,
-	.dram_odt0 = 0x00000030,
-	.dram_odt1 = 0x00000030,
-	.dram_sdba2 = 0x00000000,
-	.dram_sdclk_0 = 0x00000008,
-	.dram_sdqs0 = 0x00000038,
-	.dram_sdqs1 = 0x00000030,
-	.dram_reset = 0x00000030,
-};
-
-static struct mx6_mmdc_calibration mx6_mmcd_calib = {
-	.p0_mpwldectrl0 = 0x00070007,
-	.p0_mpdgctrl0 = 0x41490145,
-	.p0_mprddlctl = 0x40404546,
-	.p0_mpwrdlctl = 0x4040524D,
-};
-
-struct mx6_ddr_sysinfo ddr_sysinfo = {
-	.dsize = 0,
-	.cs_density = 20,
-	.ncs = 1,
-	.cs1_mirror = 0,
-	.rtt_wr = 2,
-	.rtt_nom = 1,		/* RTT_Nom = RZQ/2 */
-	.walat = 1,		/* Write additional latency */
-	.ralat = 5,		/* Read additional latency */
-	.mif3_mode = 3,		/* Command prediction working mode */
-	.bi_on = 1,		/* Bank interleaving enabled */
-	.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
-	.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
-	.ddr_type = DDR_TYPE_DDR3,
-};
-
-static struct mx6_ddr3_cfg mem_ddr = {
-	.mem_speed = 800,
-	.density = 4,
-	.width = 16,
-	.banks = 8,
-	.rowaddr = 15,
-	.coladdr = 10,
-	.pagesz = 2,
-	.trcd = 1375,
-	.trcmin = 4875,
-	.trasmin = 3500,
-};
-
-static void ccgr_init(void)
-{
-	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
-	writel(0x00c03f3f, &ccm->CCGR0);
-	writel(0xfcffff00, &ccm->CCGR1);
-	writel(0x0cffffcc, &ccm->CCGR2);
-	writel(0x3f3c3030, &ccm->CCGR3);
-	writel(0xff00fffc, &ccm->CCGR4);
-	writel(0x033f30ff, &ccm->CCGR5);
-	writel(0x00c00fff, &ccm->CCGR6);
-}
-
-static void spl_dram_init(void)
-{
-	mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
-	mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
-}
-
-void board_init_f(ulong dummy)
-{
-	/* setup AIPS and disable watchdog */
-	arch_cpu_init();
-
-	ccgr_init();
-
-	/* iomux and setup of i2c */
-	board_early_init_f();
-
-	/* setup GP timer */
-	timer_init();
-
-	/* UART clocks enabled and gd valid - init serial console */
-	preloader_console_init();
-
-	/* DDR initialization */
-	spl_dram_init();
-
-	/* Clear the BSS. */
-	memset(__bss_start, 0, __bss_end - __bss_start);
-
-	/* load/boot image from boot device */
-	board_init_r(NULL, 0);
-}
 #endif /* CONFIG_SPL_BUILD */