diff options
| author | Matthias Fuchs <matthias.fuchs@esd-electronics.com> | 2009-02-20 10:19:18 +0100 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2009-03-20 22:39:14 +0100 |
| commit | 049216f045fd8e0f45bcef121c2bb1c7d3de6988 (patch) | |
| tree | eb0cb37228f27f5fc9737c0e8e960afa8e2993c9 /board/esd/cpci405 | |
| parent | a59205d1519375d027f97a545ad642ab20fce6f8 (diff) | |
ppc4xx: Use correct io accessors for esd 405 boards
This patch replaces in/out8/16/32 macros by in/out_8/_be16/_be32
macros. Also volatile pointer references are replaced by the
new accessors.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/esd/cpci405')
| -rw-r--r-- | board/esd/cpci405/cpci405.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c index 0aca825c12..ccbe245d76 100644 --- a/board/esd/cpci405/cpci405.c +++ b/board/esd/cpci405/cpci405.c @@ -111,10 +111,10 @@ int board_early_init_f(void) * First pull fpga-prg pin low, * to disable fpga logic (on version 2 board) */ - out32(GPIO0_ODR, 0x00000000); /* no open drain pins */ - out32(GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */ - out32(GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */ - out32(GPIO0_OR, 0); /* pull prg low */ + out_be32((void *)GPIO0_ODR, 0x00000000); /* no open drain pins */ + out_be32((void *)GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */ + out_be32((void *)GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */ + out_be32((void *)GPIO0_OR, 0); /* pull prg low */ /* * Boot onboard FPGA |