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authorShaveta Leekha <shaveta@freescale.com>2013-07-02 14:43:53 +0530
committerYork Sun <yorksun@freescale.com>2013-08-09 12:41:41 -0700
commitcb033741f425c8290fdcfbe6da4ae69b504c52fa (patch)
treea922b6cf2db7c629704aac235c4a97aede5cd55a /board/freescale/b4860qds/eth_b4860qds.c
parent40f398a42b2f7509f08cfe2dd0e77aa3eeec6540 (diff)
board/b4860qds: Add support for configuring SerDes1 Refclks
1) Add support in B4860 board files for using IDT driver where IDT8T49N222A is a low phase noise Frequency Translator / Synthesizer that generate different refclks for SerDes modules, used this driver for reconfiguring SerDes1 Refclks(based on SerDes1 protocols) for CPRI to work. CPRI works on 122.88MHz and default refclks coming on board are not suitable for it 2) Move SerDes1 refclk1 source selection from eth_b4860qds.c file to b4860qds board file, as SerDes1 Refclk1 would come from PHY MUX in case of certain protocols, that have been checked here. This change would make on board SGMIIs to work 3) Add I2C addresses for IDT8T49N222A devices in board/include file 4) Add define for PCA-I2C bus multiplexer, on which IDT devices exist Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board/freescale/b4860qds/eth_b4860qds.c')
-rw-r--r--board/freescale/b4860qds/eth_b4860qds.c2
1 files changed, 0 insertions, 2 deletions
diff --git a/board/freescale/b4860qds/eth_b4860qds.c b/board/freescale/b4860qds/eth_b4860qds.c
index 19ca66e3d0..dc4ef80fc8 100644
--- a/board/freescale/b4860qds/eth_b4860qds.c
+++ b/board/freescale/b4860qds/eth_b4860qds.c
@@ -201,8 +201,6 @@ int board_eth_init(bd_t *bis)
debug("Setting phy addresses for FM1_DTSEC5: %x and"
"FM1_DTSEC6: %x\n", CONFIG_SYS_FM1_DTSEC5_PHY_ADDR,
CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
- /* Fixing Serdes clock by programming FPGA register */
- QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125);
fm_info_set_phy_address(FM1_DTSEC5,
CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC6,