diff options
| author | Tom Rini <trini@ti.com> | 2013-08-13 09:14:02 -0400 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-08-13 09:14:02 -0400 |
| commit | b98d934128bcd98106e764d2f492ac79c38ae53d (patch) | |
| tree | 5e078614fccb51f34fa8f7aa8d92c4f5f518b686 /board/freescale/bsc9132qds/bsc9132qds.c | |
| parent | 67cafc0861477bf19a587508ed13f4538c7a281e (diff) | |
| parent | 3aab0cd852d7c9565c2559a7983cbb73852bac28 (diff) | |
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'board/freescale/bsc9132qds/bsc9132qds.c')
| -rw-r--r-- | board/freescale/bsc9132qds/bsc9132qds.c | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/board/freescale/bsc9132qds/bsc9132qds.c b/board/freescale/bsc9132qds/bsc9132qds.c index 457489416a..a895e4e297 100644 --- a/board/freescale/bsc9132qds/bsc9132qds.c +++ b/board/freescale/bsc9132qds/bsc9132qds.c @@ -125,6 +125,27 @@ void board_config_serdes_mux(void) } } +/* Configure DSP DDR controller */ +void dsp_ddr_configure(void) +{ + /* + *There are separate DDR-controllers for DSP and PowerPC side DDR. + *copy the ddr controller settings from PowerPC side DDR controller + *to the DSP DDR controller as connected DDR memories are similar. + */ + ccsr_ddr_t __iomem *pa_ddr = + (ccsr_ddr_t __iomem *)CONFIG_SYS_MPC8xxx_DDR_ADDR; + ccsr_ddr_t temp_ddr; + ccsr_ddr_t __iomem *dsp_ddr = + (ccsr_ddr_t __iomem *)CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR; + + memcpy(&temp_ddr, pa_ddr, sizeof(ccsr_ddr_t)); + temp_ddr.cs0_bnds = CONFIG_SYS_DDR1_CS0_BNDS; + temp_ddr.sdram_cfg &= ~SDRAM_CFG_MEM_EN; + memcpy(dsp_ddr, &temp_ddr, sizeof(ccsr_ddr_t)); + dsp_ddr->sdram_cfg |= SDRAM_CFG_MEM_EN; +} + int board_early_init_r(void) { #ifndef CONFIG_SYS_NO_FLASH @@ -153,6 +174,7 @@ int board_early_init_r(void) 0, flash_esel+1, BOOKE_PAGESZ_64M, 1); #endif board_config_serdes_mux(); + dsp_ddr_configure(); return 0; } |