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| author | Masahiro Yamada <yamada.m@jp.panasonic.com> | 2015-01-21 15:27:48 +0900 |
|---|---|---|
| committer | Masahiro Yamada <yamada.m@jp.panasonic.com> | 2015-01-23 00:52:16 +0900 |
| commit | 0ba924a4ecfe056ab637bfa207fc26cd0248e9ac (patch) | |
| tree | e6d21e04a345fff3dd56af9da79f0828cc018df4 /board/freescale/c29xpcie/cpld.h | |
| parent | 367a0d51dbb18983f047ca43b9233a121e39b024 (diff) | |
ARM: UniPhier: add SG_MEMCONF macros for DDR channel 2
PH1-sLD3, PH1-LD6b have DDR channel 2.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Diffstat (limited to 'board/freescale/c29xpcie/cpld.h')
0 files changed, 0 insertions, 0 deletions