diff options
| author | Kumar Gala <galak@kernel.crashing.org> | 2011-01-24 23:36:17 -0600 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2011-04-04 09:24:40 -0500 |
| commit | 5cfbc458d4957a186d1433cf1c14e8f4e6d4431f (patch) | |
| tree | 96bc8fc9e7b5208e681cfee684724efb20b1af2b /board/freescale/corenet_ds/p4080ds_ddr.c | |
| parent | aa8d3fb8f4d383e7371f8f678ca3db1ca7d0ae32 (diff) | |
powerpc/85xx: Remove DATARATE_*_MHZ defines in static ddr init
Rather than having #defines DATARATE_*_MHZ, lets just match what we do on
the SPD code and convert the DDR frequency into MHZ and just compare
with a constant.
Based on patch from Poonam Aggrwal.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'board/freescale/corenet_ds/p4080ds_ddr.c')
| -rw-r--r-- | board/freescale/corenet_ds/p4080ds_ddr.c | 24 |
1 files changed, 9 insertions, 15 deletions
diff --git a/board/freescale/corenet_ds/p4080ds_ddr.c b/board/freescale/corenet_ds/p4080ds_ddr.c index 4ad89ff48a..ccb9da832c 100644 --- a/board/freescale/corenet_ds/p4080ds_ddr.c +++ b/board/freescale/corenet_ds/p4080ds_ddr.c @@ -1,5 +1,5 @@ /* - * Copyright 2009-2010 Freescale Semiconductor, Inc. + * Copyright 2009-2011 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -9,12 +9,6 @@ #include <common.h> #include <asm/fsl_ddr_sdram.h> -#define DATARATE_800MHZ 800000000 -#define DATARATE_900MHZ 900000000 -#define DATARATE_1000MHZ 1000000000 -#define DATARATE_1200MHZ 1200000000 -#define DATARATE_1300MHZ 1300000000 - #define CONFIG_SYS_DDR_TIMING_3_1200 0x01030000 #define CONFIG_SYS_DDR_TIMING_0_1200 0xCC550104 #define CONFIG_SYS_DDR_TIMING_1_1200 0x868FAA45 @@ -340,17 +334,17 @@ fsl_ddr_cfg_regs_t ddr_cfg_regs_1200_2nd = { }; fixed_ddr_parm_t fixed_ddr_parm_0[] = { - {DATARATE_800MHZ, DATARATE_900MHZ, &ddr_cfg_regs_800}, - {DATARATE_900MHZ, DATARATE_1000MHZ, &ddr_cfg_regs_900}, - {DATARATE_1000MHZ, DATARATE_1200MHZ, &ddr_cfg_regs_1000}, - {DATARATE_1200MHZ, DATARATE_1300MHZ, &ddr_cfg_regs_1200}, + {800, 900, &ddr_cfg_regs_800}, + {900, 1000, &ddr_cfg_regs_900}, + {1000, 1200, &ddr_cfg_regs_1000}, + {1200, 1300, &ddr_cfg_regs_1200}, {0, 0, NULL} }; fixed_ddr_parm_t fixed_ddr_parm_1[] = { - {DATARATE_800MHZ, DATARATE_900MHZ, &ddr_cfg_regs_800_2nd}, - {DATARATE_900MHZ, DATARATE_1000MHZ, &ddr_cfg_regs_900_2nd}, - {DATARATE_1000MHZ, DATARATE_1200MHZ, &ddr_cfg_regs_1000_2nd}, - {DATARATE_1200MHZ, DATARATE_1300MHZ, &ddr_cfg_regs_1200_2nd}, + {800, 900, &ddr_cfg_regs_800_2nd}, + {900, 1000, &ddr_cfg_regs_900_2nd}, + {1000, 1200, &ddr_cfg_regs_1000_2nd}, + {1200, 1300, &ddr_cfg_regs_1200_2nd}, {0, 0, NULL} }; |