diff options
| author | Tom Rini <trini@ti.com> | 2013-08-13 09:14:02 -0400 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-08-13 09:14:02 -0400 |
| commit | b98d934128bcd98106e764d2f492ac79c38ae53d (patch) | |
| tree | 5e078614fccb51f34fa8f7aa8d92c4f5f518b686 /board/freescale/corenet_ds | |
| parent | 67cafc0861477bf19a587508ed13f4538c7a281e (diff) | |
| parent | 3aab0cd852d7c9565c2559a7983cbb73852bac28 (diff) | |
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'board/freescale/corenet_ds')
| -rw-r--r-- | board/freescale/corenet_ds/corenet_ds.c | 17 | ||||
| -rw-r--r-- | board/freescale/corenet_ds/ddr.c | 4 |
2 files changed, 5 insertions, 16 deletions
diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c index fffb0c817a..60e2100af3 100644 --- a/board/freescale/corenet_ds/corenet_ds.c +++ b/board/freescale/corenet_ds/corenet_ds.c @@ -27,8 +27,10 @@ int checkboard (void) { u8 sw; struct cpu_type *cpu = gd->arch.cpu; - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; +#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) || \ + defined(CONFIG_P5040DS) unsigned int i; +#endif static const char * const freq[] = {"100", "125", "156.25", "212.5" }; printf("Board: %sDS, ", cpu->name); @@ -47,19 +49,6 @@ int checkboard (void) else printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH); - /* Display the RCW, so that no one gets confused as to what RCW - * we're actually using for this boot. - */ - puts("Reset Configuration Word (RCW):"); - for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { - u32 rcw = in_be32(&gur->rcwsr[i]); - - if ((i % 4) == 0) - printf("\n %08x:", i * 4); - printf(" %08x", rcw); - } - puts("\n"); - /* Display the actual SERDES reference clocks as configured by the * dip switches on the board. Note that the SWx registers could * technically be set to force the reference clocks to match the diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c index da284cde95..517e87ff4c 100644 --- a/board/freescale/corenet_ds/ddr.c +++ b/board/freescale/corenet_ds/ddr.c @@ -56,14 +56,14 @@ phys_size_t fixed_sdram(void) ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN; - fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0); + fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0); #if (CONFIG_NUM_DDR_CONTROLLERS == 2) memcpy(&ddr_cfg_regs, fixed_ddr_parm_1[i].ddr_settings, sizeof(ddr_cfg_regs)); ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN; - fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 1); + fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 1, 0); #endif /* |