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author | Sherry Sun <sherry.sun@nxp.com> | 2020-01-20 11:13:14 +0800 |
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committer | Peng Fan <peng.fan@nxp.com> | 2020-07-14 15:23:46 +0800 |
commit | f3acb02386f4d5df6e5b5eb96302f169c28933db (patch) | |
tree | 1eee8b632a42d6dc1c45c3560773347e997b49e3 /board/freescale/imx8mp_evk | |
parent | 1eb325af16e2a6987f4aa91e563ad6c160f64a5a (diff) |
drivers: ddr: imx8mp: Add inline ECC feature support
the DRAM Controller in i.MX8MP will support a feature called "Inline ECC".
This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and
DDR3L). When this feature is enabled by software, the DRAM Controller
reserves 12.5% of DRAM capacity for ECC information, and presents only
the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to
the rest of the SoC.
The DRAM memory can be divided into 8 regions so that if a use case only
requires ECC protection on a subset of memory, then only that subset of
memory need support inline ECC. If this occurs, then there is no
performance penalty accessing the non-ECC-protected memory (no need to
access ECC for this portion of the memory map). This is all configured
with the DRAM Controller.
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'board/freescale/imx8mp_evk')
0 files changed, 0 insertions, 0 deletions