diff options
| author | Xiaoliang Yang <xiaoliang.yang@nxp.com> | 2016-09-14 11:36:14 +0800 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-10-06 09:55:08 -0700 |
| commit | f85a8e8d1db374d894afc03504a0eead1de99f74 (patch) | |
| tree | 19af1b973cc4b09f23a15cd26400bcf7fb88845c /board/freescale/ls1021atwr | |
| parent | b259732d36ccdc911e5b3ed83bd55aae90a43532 (diff) | |
armv7: LS1021a: enable i-cache in start.S
Delete CONFIG_SKIP_LOWLEVEL_INIT define in ls1021atwr.h and
ls1021aqds.h can let it run cpu_init_cp15 to enable i-cache. First
stage of u-boot can run faster after that. There is a description
about skip lowlevel init in board/freescale/ls1021atwr/README.
Signed-off-by: Xiaoliang Yang <xiaoliang.yang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'board/freescale/ls1021atwr')
| -rw-r--r-- | board/freescale/ls1021atwr/README | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/board/freescale/ls1021atwr/README b/board/freescale/ls1021atwr/README index d2821cbb6b..896a659476 100644 --- a/board/freescale/ls1021atwr/README +++ b/board/freescale/ls1021atwr/README @@ -107,3 +107,9 @@ Start Address End Address Description Size 0x00_4000_0000 0x00_5FFF_FFFF QSPI 512MB 0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB 0x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB + +LS1021a rev1.0 Soc specific Options/Settings +-------------------------------------------- +If the LS1021a Soc is rev1.0, you need modify the configure file. +Add the following define in include/configs/ls1021atwr.h: +#define CONFIG_SKIP_LOWLEVEL_INIT |