diff options
| author | Sumit Garg <sumit.garg@nxp.com> | 2017-03-23 13:48:17 +0530 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2017-04-17 09:03:30 -0700 |
| commit | b7c19ea1ca7d3a02b8aa1e0f756ca60951fa367e (patch) | |
| tree | 73af07e0943e3d9da865e6f5684995d493d99353 /board/freescale/ls1046aqds/ls1046aqds.c | |
| parent | b3635f57d94c366bd94f9f8010024cd6a2d6b272 (diff) | |
armv8: LS1046AQDS: Add NOR Secure Boot Target
Add NOR secure boot target. Also enable sec init.
Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'board/freescale/ls1046aqds/ls1046aqds.c')
| -rw-r--r-- | board/freescale/ls1046aqds/ls1046aqds.c | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c index 69fc15b681..58ce75acf6 100644 --- a/board/freescale/ls1046aqds/ls1046aqds.c +++ b/board/freescale/ls1046aqds/ls1046aqds.c @@ -22,6 +22,7 @@ #include <fsl_csu.h> #include <fsl_esdhc.h> #include <fsl_ifc.h> +#include <fsl_sec.h> #include <spl.h> #include "../common/vid.h" @@ -266,6 +267,24 @@ int board_init(void) if (adjust_vdd(0)) printf("Warning: Adjusting core voltage failed.\n"); +#ifdef CONFIG_SECURE_BOOT + /* + * In case of Secure Boot, the IBR configures the SMMU + * to allow only Secure transactions. + * SMMU must be reset in bypass mode. + * Set the ClientPD bit and Clear the USFCFG Bit + */ + u32 val; + val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); + out_le32(SMMU_SCR0, val); + val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); + out_le32(SMMU_NSCR0, val); +#endif + +#ifdef CONFIG_FSL_CAAM + sec_init(); +#endif + return 0; } |