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| author | Tom Rini <trini@konsulko.com> | 2016-04-06 14:17:22 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-04-06 14:17:22 -0400 |
| commit | 43d3fb5c0609a76409e7859a2a5800670c7b5bd2 (patch) | |
| tree | 562ebcc0e6a22077140b10efce77f44340b819ac /board/freescale/ls2080ardb/ddr.c | |
| parent | 46a16bd895144617575c788d9c2554aeef76ac44 (diff) | |
| parent | 3c1d218a1d3048fb576677c47eab43049d0b7778 (diff) | |
Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq
Diffstat (limited to 'board/freescale/ls2080ardb/ddr.c')
| -rw-r--r-- | board/freescale/ls2080ardb/ddr.c | 27 |
1 files changed, 15 insertions, 12 deletions
diff --git a/board/freescale/ls2080ardb/ddr.c b/board/freescale/ls2080ardb/ddr.c index 6c191738ec..a04d21be13 100644 --- a/board/freescale/ls2080ardb/ddr.c +++ b/board/freescale/ls2080ardb/ddr.c @@ -7,6 +7,7 @@ #include <common.h> #include <fsl_ddr_sdram.h> #include <fsl_ddr_dimm_params.h> +#include <asm/arch/soc.h> #include "ddr.h" DECLARE_GLOBAL_DATA_PTR; @@ -201,22 +202,24 @@ void dram_init_banksize(void) } #ifdef CONFIG_SYS_DP_DDR_BASE_PHY - /* initialize DP-DDR here */ - puts("DP-DDR: "); - /* - * DDR controller use 0 as the base address for binding. - * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. - */ - dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY, + if (soc_has_dp_ddr()) { + /* initialize DP-DDR here */ + puts("DP-DDR: "); + /* + * DDR controller use 0 as the base address for binding. + * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. + */ + dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY, CONFIG_DP_DDR_CTRL, CONFIG_DP_DDR_NUM_CTRLS, CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR, NULL, NULL, NULL); - if (dp_ddr_size) { - gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE; - gd->bd->bi_dram[2].size = dp_ddr_size; - } else { - puts("Not detected"); + if (dp_ddr_size) { + gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE; + gd->bd->bi_dram[2].size = dp_ddr_size; + } else { + puts("Not detected"); + } } #endif } |