diff options
| author | Priyanka Jain <priyanka.jain@nxp.com> | 2017-04-27 15:08:07 +0530 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2017-05-23 09:47:08 -0700 |
| commit | 3049a583f343a71ead9d7cb33f0ab6cecfbbaa12 (patch) | |
| tree | 8cd1822e41925299bd43a63d213e0be10bf2ceff /board/freescale/ls2080ardb/ls2080ardb.c | |
| parent | e809e747996b00acd0ffc833999e97a3a21ddfac (diff) | |
armv8: ls2080ardb: Add LS2081ARDB board support
LS2081ARDB board is similar to LS2080ARDB board with few differences
It hosts LS2081A SoC
Default boot source is QSPI-boot
It does not have IFC interface
RTC and QSPI flash device are different
It provides QIXIS access via I2C
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'board/freescale/ls2080ardb/ls2080ardb.c')
| -rw-r--r-- | board/freescale/ls2080ardb/ls2080ardb.c | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index 10e8ea4e42..df2d768718 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -68,6 +68,44 @@ int checkboard(void) cpu_name(buf); printf("Board: %s-RDB, ", buf); +#ifdef CONFIG_TARGET_LS2081ARDB +#ifdef CONFIG_FSL_QIXIS + sw = QIXIS_READ(arch); + printf("Board Arch: V%d, ", sw >> 4); + printf("Board version: %c, ", (sw & 0xf) + 'A'); + + sw = QIXIS_READ(brdcfg[0]); + sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT; + switch (sw) { + case 0: + puts("boot from QSPI DEV#0\n"); + puts("QSPI_CSA_1 mapped to QSPI DEV#1\n"); + break; + case 1: + puts("boot from QSPI DEV#1\n"); + puts("QSPI_CSA_1 mapped to QSPI DEV#0\n"); + break; + case 2: + puts("boot from QSPI EMU\n"); + puts("QSPI_CSA_1 mapped to QSPI DEV#0\n"); + break; + case 3: + puts("boot from QSPI EMU\n"); + puts("QSPI_CSA_1 mapped to QSPI DEV#1\n"); + break; + case 4: + puts("boot from QSPI DEV#0\n"); + puts("QSPI_CSA_1 mapped to QSPI EMU\n"); + break; + default: + printf("invalid setting of SW%u\n", sw); + break; + } +#endif + puts("SERDES1 Reference : "); + printf("Clock1 = 100MHz "); + printf("Clock2 = 161.13MHz"); +#else #ifdef CONFIG_FSL_QIXIS sw = QIXIS_READ(arch); printf("Board Arch: V%d, ", sw >> 4); @@ -88,6 +126,7 @@ int checkboard(void) puts("SERDES1 Reference : "); printf("Clock1 = 156.25MHz "); printf("Clock2 = 156.25MHz"); +#endif puts("\nSERDES2 Reference : "); printf("Clock1 = 100MHz "); @@ -209,6 +248,9 @@ int board_init(void) int board_early_init_f(void) { +#ifdef CONFIG_SYS_I2C_EARLY_INIT + i2c_early_init_f(); +#endif fsl_lsch3_early_init_f(); return 0; } @@ -216,6 +258,11 @@ int board_early_init_f(void) int misc_init_r(void) { #ifdef CONFIG_FSL_QIXIS + /* + * LS2081ARDB has smart voltage translator which needs + * to be programmed as below + */ +#ifndef CONFIG_TARGET_LS2081ARDB u8 sw; sw = QIXIS_READ(arch); @@ -225,12 +272,15 @@ int misc_init_r(void) * by setting GPIO4_10 output to zero */ if ((sw & 0xf) == 0x5) { +#endif out_le32(GPIO4_GPDIR_ADDR, (1 << 21 | in_le32(GPIO4_GPDIR_ADDR))); out_le32(GPIO4_GPDAT_ADDR, (~(1 << 21) & in_le32(GPIO4_GPDAT_ADDR))); +#ifndef CONFIG_TARGET_LS2081ARDB } #endif +#endif if (hwconfig("sdhc")) config_board_mux(MUX_TYPE_SDHC); @@ -350,6 +400,7 @@ void update_spd_address(unsigned int ctrl_num, unsigned int slot, unsigned int *addr) { +#ifndef CONFIG_TARGET_LS2081ARDB #ifdef CONFIG_FSL_QIXIS u8 sw; @@ -361,4 +412,5 @@ void update_spd_address(unsigned int ctrl_num, *addr = SPD_EEPROM_ADDRESS3; } #endif +#endif } |