diff options
| author | Prabhakar Kushwaha <prabhakar@freescale.com> | 2015-08-07 18:01:51 +0530 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-09-01 21:38:46 -0500 |
| commit | cf7ee6c4e37ea4bc56df4b2e543874ec68b33bc7 (patch) | |
| tree | c5a450b669bba5eba69d53ff38a6ebbe467ef008 /board/freescale/ls2085aqds/README | |
| parent | 4c2620dd71fdba98e5a6c1e7b8326365307dae57 (diff) | |
armv8: ls2085qds: Add support of X-QSGMII-16PORT riser card
The X-QSGMII-16PORT is a 4xQSGMII/8xSGMII riser card with eighth SerDes
interfaces implemented in PCIe form factor board.
It supports followings
- Card can operate with up to 4 QSGMII lane simultaneously
- Card can operate with up to 8 SGMII lane simultaneously
Add support of X-QSGMII-16PORT riser card.
This patch also take care of back-ward compatiblity with old SGMII rise cards
used on LS2085QDS Platform.
Signed-off-by: King Chung Lo@freescale.com <KingChungLo@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board/freescale/ls2085aqds/README')
| -rw-r--r-- | board/freescale/ls2085aqds/README | 81 |
1 files changed, 81 insertions, 0 deletions
diff --git a/board/freescale/ls2085aqds/README b/board/freescale/ls2085aqds/README index 11b2e79945..e4a6f69bfc 100644 --- a/board/freescale/ls2085aqds/README +++ b/board/freescale/ls2085aqds/README @@ -146,3 +146,84 @@ below: earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m hugepages=16 mem=2048M' + +X-QSGMII-16PORT riser card +---------------------------- +The X-QSGMII-16PORT is a 4xQSGMII/8xSGMII riser card with eighth SerDes +interfaces implemented in PCIe form factor board. +It supports followings + - Card can operate with up to 4 QSGMII lane simultaneously + - Card can operate with up to 8 SGMII lane simultaneously + +Supported card configuration + - CSEL : ON ON ON ON + - MSEL1 : ON ON ON ON OFF OFF OFF OFF + - MSEL2 : OFF OFF OFF OFF ON ON ON ON + +To enable this card: modify hwconfig to add "xqsgmii" variable. + +Supported PHY addresses during SGMII: +#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0 +#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2 +#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4 +#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6 +#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8 +#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa +#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc +#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe + +Mapping DPMACx to PHY during QSGMII +DPMAC1 -> PHY1-P0 +DPMAC2 -> PHY2-P0 +DPMAC3 -> PHY3-P0 +DPMAC4 -> PHY4-P0 +DPMAC5 -> PHY3-P2 +DPMAC6 -> PHY1-P2 +DPMAC7 -> PHY4-P1 +DPMAC8 -> PHY2-P2 +DPMAC9 -> PHY1-P0 +DPMAC10 -> PHY2-P0 +DPMAC11 -> PHY3-P0 +DPMAC12 -> PHY4-P0 +DPMAC13 -> PHY3-P2 +DPMAC14 -> PHY1-P2 +DPMAC15 -> PHY4-P1 +DPMAC16 -> PHY2-P2 + + +Supported PHY address during QSGMII +#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0 +#define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1 +#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2 +#define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3 +#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4 +#define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5 +#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6 +#define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7 +#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8 +#define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9 +#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa +#define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb +#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc +#define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd +#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe +#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf + +Mapping DPMACx to PHY during QSGMII +DPMAC1 -> PHY1-P3 +DPMAC2 -> PHY1-P2 +DPMAC3 -> PHY1-P1 +DPMAC4 -> PHY1-P0 +DPMAC5 -> PHY2-P3 +DPMAC6 -> PHY2-P2 +DPMAC7 -> PHY2-P1 +DPMAC8 -> PHY2-P0 +DPMAC9 -> PHY3-P0 +DPMAC10 -> PHY3-P1 +DPMAC11 -> PHY3-P2 +DPMAC12 -> PHY3-P3 +DPMAC13 -> PHY4-P0 +DPMAC14 -> PHY4-P1 +DPMAC15 -> PHY4-P2 +DPMAC16 -> PHY4-P3 + |