diff options
| author | Fabio Estevam <fabio.estevam@nxp.com> | 2016-09-26 09:14:25 -0300 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2016-10-04 12:01:14 +0200 |
| commit | 3b30eece271cfc4096c2d20048c89e8bed0bbbfd (patch) | |
| tree | 6fbcaaeffab10ebe96a52885e2ad936829661253 /board/freescale/mpc8610hpcd | |
| parent | 5cca52a4cad8461457d938512829eeb9c68377ff (diff) | |
mx6sabresd: Make SPL DDR configuration to match the DCD table
When using SPL on i.mx6 we frequently notice some DDR initialization
mismatches between the SPL code and the non-SPL code.
This causes stability issues like the ones reported at 7dbda25ecd6d7c
("mx6ul_14x14_evk: Pass refsel and refr fields to avoid hang") and also:
http://lists.denx.de/pipermail/u-boot/2016-September/266355.html .
As the non-SPL code have been tested for long time and proves to be reliable,
let's configure the DDR in the exact same way as the non-SPL case.
The idea is simple: just use the DCD table and write directly to the DDR
registers.
Retrieved the DCD tables from:
board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg
and
board/freescale/mx6sabresd/mx6qp.cfg
(NXP U-Boot branch imx_v2015.04_4.1.15_1.0.0_ga)
This method makes it easier for people converting from non-SPL to SPL code.
Other benefit is that the SPL binary size is reduced from 44 kB to 39.9 kB.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Diffstat (limited to 'board/freescale/mpc8610hpcd')
0 files changed, 0 insertions, 0 deletions