diff options
| author | Wolfgang Denk <wd@denx.de> | 2008-11-02 16:14:22 +0100 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-11-02 16:14:22 +0100 |
| commit | 3cbd823116ea8b7c654e275a8c2fca87cd1f5dc5 (patch) | |
| tree | 8cda4daa32f477368ab3690cdfc879c610ef1b03 /board/freescale/mpc8641hpcn/ddr.c | |
| parent | 3ec53148eb68ddfb0c3311fb4c06cd2bd0ef3eeb (diff) | |
Coding Style cleanup, update CHANGELOG
Signed-off-by: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'board/freescale/mpc8641hpcn/ddr.c')
| -rw-r--r-- | board/freescale/mpc8641hpcn/ddr.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/board/freescale/mpc8641hpcn/ddr.c b/board/freescale/mpc8641hpcn/ddr.c index 517c6ee0e9..3789b5442e 100644 --- a/board/freescale/mpc8641hpcn/ddr.c +++ b/board/freescale/mpc8641hpcn/ddr.c @@ -47,12 +47,12 @@ void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, } typedef struct { - u32 datarate_mhz_low; - u32 datarate_mhz_high; - u32 n_ranks; - u32 clk_adjust; - u32 cpo; - u32 write_data_delay; + u32 datarate_mhz_low; + u32 datarate_mhz_high; + u32 n_ranks; + u32 clk_adjust; + u32 cpo; + u32 write_data_delay; } board_specific_parameters_t; /* XXX: these values need to be checked for all interleaving modes. */ @@ -84,7 +84,7 @@ const board_specific_parameters_t board_specific_parameters[2][16] = { { /* memory controller 1 */ - /* lo| hi| num| clk| cpo|wrdata */ + /* lo| hi| num| clk| cpo|wrdata */ /* mhz| mhz|ranks|adjst| | delay */ { 0, 333, 4, 7, 7, 3}, {334, 400, 4, 7, 9, 3}, @@ -129,7 +129,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, if (i&1) { /* odd CS */ popts->cs_local_opts[i].odt_rd_cfg = 0; popts->cs_local_opts[i].odt_wr_cfg = 0; - } else { /* even CS */ + } else { /* even CS */ if ((CONFIG_DIMM_SLOTS_PER_CTLR == 2) && (pdimm[i/2].n_ranks != 0)) { popts->cs_local_opts[i].odt_rd_cfg = 3; |