diff options
| author | Ye Li <ye.li@nxp.com> | 2019-05-15 09:56:51 +0000 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2019-07-19 20:14:50 +0200 |
| commit | 72a9414bd41b12fb140315d03596a30ee0bf882d (patch) | |
| tree | 5e1a55100a3fa76edc2db32dcae7776598938d9a /board/freescale/mx7ulp_evk/plugin.S | |
| parent | 2528a666aea244b20abf7b387039b10b1d8c2d76 (diff) | |
mx7ulp: Fix APLL num and denom setting issue
For the current APLL setting, as we want the APLL PFD0 to meet DDR clock 320Mhz requirement.
We set MULT to 20, NUM to 4 and DENOM to 2, to get final 22 multiplier. But according to the RM,
the NUM should always be less than the DENOM. So our setting violates the rule.
Actually the ROM has already set the MULT to 22 and leave NUM/DENOM in default value. The calculated APLL PFD0 clock
is 318.9888Mhz, which also meet the DDR requirement.
To fix the issue, we remove the PLL settings in DCD to use default value from ROM, and only set the PFD0 FRAC.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'board/freescale/mx7ulp_evk/plugin.S')
| -rw-r--r-- | board/freescale/mx7ulp_evk/plugin.S | 19 |
1 files changed, 1 insertions, 18 deletions
diff --git a/board/freescale/mx7ulp_evk/plugin.S b/board/freescale/mx7ulp_evk/plugin.S index 082b2beaa3..802ae5f49a 100644 --- a/board/freescale/mx7ulp_evk/plugin.S +++ b/board/freescale/mx7ulp_evk/plugin.S @@ -13,26 +13,9 @@ ldr r2, =0x403e0000 ldr r3, =0x01000020 str r3, [r2, #0x40] - ldr r3, =0x01000000 - str r3, [r2, #0x500] + ldr r3, =0x80808080 str r3, [r2, #0x50c] - ldr r3, =0x00140000 - str r3, [r2, #0x508] - ldr r3, =0x00000004 - str r3, [r2, #0x510] - ldr r3, =0x00000002 - str r3, [r2, #0x514] - ldr r3, =0x00000001 - str r3, [r2, #0x500] - - ldr r3, =0x01000000 -wait1: - ldr r4, [r2, #0x500] - and r4, r3 - cmp r4, r3 - bne wait1 - ldr r3, =0x8080801E str r3, [r2, #0x50c] |