Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

5 files changed, 267 insertions, 13 deletions

diff --git a/board/freescale/p1_p2_rdb/Makefile b/board/freescale/p1_p2_rdb/Makefile
index f7b568a021..a97bf45f00 100644
--- a/board/freescale/p1_p2_rdb/Makefile
+++ b/board/freescale/p1_p2_rdb/Makefile
@@ -4,8 +4,27 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+
+obj-y	+= spl_minimal.o tlb.o law.o
+
+else
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+else
 obj-y	+= p1_p2_rdb.o
+obj-$(CONFIG_PCI)  += pci.o
+endif
 obj-y	+= ddr.o
 obj-y	+= law.o
-obj-$(CONFIG_PCI)  += pci.o
 obj-y	+= tlb.o
+
+endif
diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c
index 17d3beac39..98ee5f1021 100644
--- a/board/freescale/p1_p2_rdb/ddr.c
+++ b/board/freescale/p1_p2_rdb/ddr.c
@@ -180,27 +180,22 @@ fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
 
 phys_size_t fixed_sdram (void)
 {
-	char buf[32];
 	fsl_ddr_cfg_regs_t ddr_cfg_regs;
 	size_t ddr_size;
 	struct cpu_type *cpu;
 	ulong ddr_freq, ddr_freq_mhz;
 
 	cpu = gd->arch.cpu;
-	/* P1020 and it's derivatives support max 32bit DDR width */
-	if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1011) {
-		ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2);
-	} else {
-		ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-	}
+
+	ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+
 #if defined(CONFIG_SYS_RAMBOOT)
 	return ddr_size;
 #endif
 	ddr_freq = get_ddr_freq(0);
 	ddr_freq_mhz = ddr_freq / 1000000;
 
-	printf("Configuring DDR for %s MT/s data rate\n",
-				strmhz(buf, ddr_freq));
+	printf("Configuring DDR for %ld T/s data rate\n", ddr_freq);
 
 	if(ddr_freq_mhz <= 400)
 		memcpy(&ddr_cfg_regs, &ddr_cfg_regs_400, sizeof(ddr_cfg_regs));
@@ -211,8 +206,7 @@ phys_size_t fixed_sdram (void)
 	else if(ddr_freq_mhz <= 800)
 		memcpy(&ddr_cfg_regs, &ddr_cfg_regs_800, sizeof(ddr_cfg_regs));
 	else
-		panic("Unsupported DDR data rate %s MT/s data rate\n",
-					strmhz(buf, ddr_freq));
+		panic("Unsupported DDR data rate %ld T/s\n", ddr_freq);
 
 	/* P1020 and it's derivatives support max 32bit DDR width */
 	if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1011) {
diff --git a/board/freescale/p1_p2_rdb/spl.c b/board/freescale/p1_p2_rdb/spl.c
new file mode 100644
index 0000000000..f30c5fe3e6
--- /dev/null
+++ b/board/freescale/p1_p2_rdb/spl.c
@@ -0,0 +1,141 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <nand.h>
+#include <i2c.h>
+#include <fsl_esdhc.h>
+#include <spi_flash.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define SYSCLK_MASK	0x00200000
+#define BOARDREV_MASK	0x10100000
+
+#define SYSCLK_66	66666666
+#define SYSCLK_100	100000000
+
+unsigned long get_board_sys_clk(ulong dummy)
+{
+	ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+	u32 val_gpdat, sysclk_gpio;
+
+	val_gpdat = in_be32(&pgpio->gpdat);
+	sysclk_gpio = val_gpdat & SYSCLK_MASK;
+
+	if (sysclk_gpio == 0)
+		return SYSCLK_66;
+	else
+		return SYSCLK_100;
+
+	return 0;
+}
+
+phys_size_t get_effective_memsize(void)
+{
+	return CONFIG_SYS_L2_SIZE;
+}
+
+void board_init_f(ulong bootflag)
+{
+	u32 plat_ratio, bus_clk;
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+	console_init_f();
+
+	/* Set pmuxcr to allow both i2c1 and i2c2 */
+	setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000);
+	setbits_be32(&gur->pmuxcr,
+		     in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
+
+	/* Read back the register to synchronize the write. */
+	in_be32(&gur->pmuxcr);
+
+#ifdef CONFIG_SPL_SPI_BOOT
+	clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
+#endif
+
+	/* initialize selected port with appropriate baud rate */
+	plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+	plat_ratio >>= 1;
+	bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+	gd->bus_clk = bus_clk;
+
+	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+		     bus_clk / 16 / CONFIG_BAUDRATE);
+#ifdef CONFIG_SPL_MMC_BOOT
+	puts("\nSD boot...\n");
+#elif defined(CONFIG_SPL_SPI_BOOT)
+	puts("\nSPI Flash boot...\n");
+#endif
+
+	/* copy code to RAM and jump to it - this should not return */
+	/* NOTE - code has to be copied out of NAND buffer before
+	 * other blocks can be read.
+	 */
+	relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+	/* Pointer is writable since we allocated a register for it */
+	gd = (gd_t *)CONFIG_SPL_GD_ADDR;
+	bd_t *bd;
+
+	memset(gd, 0, sizeof(gd_t));
+	bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
+	memset(bd, 0, sizeof(bd_t));
+	gd->bd = bd;
+	bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
+	bd->bi_memsize = CONFIG_SYS_L2_SIZE;
+
+	probecpu();
+	get_clocks();
+	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+			CONFIG_SPL_RELOC_MALLOC_SIZE);
+
+#ifdef CONFIG_SPL_MMC_BOOT
+	mmc_initialize(bd);
+#endif
+	/* relocate environment function pointers etc. */
+#ifdef CONFIG_SPL_NAND_BOOT
+	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+			    (uchar *)CONFIG_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_NAND_BOOT
+	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+			    (uchar *)CONFIG_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_MMC_BOOT
+	mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+			   (uchar *)CONFIG_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_SPI_BOOT
+	spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+			   (uchar *)CONFIG_ENV_ADDR);
+#endif
+
+	gd->env_addr  = (ulong)(CONFIG_ENV_ADDR);
+	gd->env_valid = 1;
+
+	gd->ram_size = initdram(0);
+#ifdef CONFIG_SPL_NAND_BOOT
+	puts("Tertiary program loader running in sram...");
+#else
+	puts("Second program loader running in sram...\n");
+#endif
+
+#ifdef CONFIG_SPL_MMC_BOOT
+	mmc_boot();
+#elif defined(CONFIG_SPL_SPI_BOOT)
+	spi_boot();
+#elif defined(CONFIG_SPL_NAND_BOOT)
+	nand_boot();
+#endif
+}
diff --git a/board/freescale/p1_p2_rdb/spl_minimal.c b/board/freescale/p1_p2_rdb/spl_minimal.c
new file mode 100644
index 0000000000..96a4d1cb0a
--- /dev/null
+++ b/board/freescale/p1_p2_rdb/spl_minimal.c
@@ -0,0 +1,84 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <asm/io.h>
+#include <nand.h>
+#include <linux/compiler.h>
+#include <asm/fsl_law.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+#define SYSCLK_MASK	0x00200000
+#define BOARDREV_MASK	0x10100000
+
+#define SYSCLK_66	66666666
+#define SYSCLK_100	100000000
+
+unsigned long get_board_sys_clk(ulong dummy)
+{
+	ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+	u32 val_gpdat, sysclk_gpio;
+
+	val_gpdat = in_be32(&pgpio->gpdat);
+	sysclk_gpio = val_gpdat & SYSCLK_MASK;
+
+	if (sysclk_gpio == 0)
+		return SYSCLK_66;
+	else
+		return SYSCLK_100;
+
+	return 0;
+}
+
+void board_init_f(ulong bootflag)
+{
+	u32 plat_ratio;
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
+	set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
+	set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
+#endif
+
+	/* initialize selected port with appropriate baud rate */
+	plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+	plat_ratio >>= 1;
+	gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+		     gd->bus_clk / 16 / CONFIG_BAUDRATE);
+
+	puts("\nNAND boot... ");
+
+	/* copy code to RAM and jump to it - this should not return */
+	/* NOTE - code has to be copied out of NAND buffer before
+	 * other blocks can be read.
+	 */
+	relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+	puts("\nSecond program loader running in sram...");
+	nand_boot();
+}
+
+void putc(char c)
+{
+	if (c == '\n')
+		NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
+
+	NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
+}
+
+void puts(const char *str)
+{
+	while (*str)
+		putc(*str++);
+}
diff --git a/board/freescale/p1_p2_rdb/tlb.c b/board/freescale/p1_p2_rdb/tlb.c
index bc98972e33..73f5729ef5 100644
--- a/board/freescale/p1_p2_rdb/tlb.c
+++ b/board/freescale/p1_p2_rdb/tlb.c
@@ -37,6 +37,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 1, BOOKE_PAGESZ_1M, 1),
 
+#ifndef CONFIG_SPL_BUILD
 	/* W**G* - Flash/promjet, localbus */
 	/* This will be changed to *I*G* after relocation to RAM. */
 	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
@@ -55,6 +56,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 			0, 4, BOOKE_PAGESZ_256K, 1),
 
 #endif /* #if defined(CONFIG_PCI) */
+#endif
 	/* *I*G - NAND */
 	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@@ -65,7 +67,21 @@ struct fsl_e_tlb_entry tlb_table[] = {
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 6, BOOKE_PAGESZ_1M, 1),
 
-#if defined(CONFIG_SYS_RAMBOOT)
+#ifdef CONFIG_SYS_INIT_L2_ADDR
+	/* *I*G - L2SRAM */
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+		      0, 11, BOOKE_PAGESZ_256K, 1),
+#if CONFIG_SYS_L2_SIZE >= (256 << 10)
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
+		      CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 12, BOOKE_PAGESZ_256K, 1),
+#endif
+#endif
+
+#if defined(CONFIG_SYS_RAMBOOT) || \
+	(defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
 			MAS3_SX|MAS3_SW|MAS3_SR, 0,
 			0, 7, BOOKE_PAGESZ_1G, 1)