Move ICS CLK chip frequency calculation code into a common board library

We have several boards that use the same ICS307 CLK chip to drive the
System clock and DDR clock.  Move the code into a common location so we
share it.

Convert the P2020DS board as the first to use the new common ICS307
code.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Timur Tabi <timur@freescale.com>

1 files changed, 0 insertions, 149 deletions

diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c
index f0ff209c0c..be4b2eb478 100644
--- a/board/freescale/p2020ds/p2020ds.c
+++ b/board/freescale/p2020ds/p2020ds.c
@@ -313,155 +313,6 @@ int board_early_init_r(void)
 	return 0;
 }
 
-#ifdef CONFIG_GET_CLK_FROM_ICS307
-/* decode S[0-2] to Output Divider (OD) */
-static unsigned char ics307_S_to_OD[] = {
-	10, 2, 8, 4, 5, 7, 3, 6
-};
-
-/* Calculate frequency being generated by ICS307-02 clock chip based upon
- * the control bytes being programmed into it. */
-/* XXX: This function should probably go into a common library */
-static unsigned long
-ics307_clk_freq(unsigned char cw0, unsigned char cw1, unsigned char cw2)
-{
-	const unsigned long InputFrequency = CONFIG_ICS307_REFCLK_HZ;
-	unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
-	unsigned long RDW = cw2 & 0x7F;
-	unsigned long OD = ics307_S_to_OD[cw0 & 0x7];
-	unsigned long freq;
-
-	/* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */
-
-	/* cw0:  C1 C0 TTL F1 F0 S2 S1 S0
-	 * cw1:  V8 V7 V6 V5 V4 V3 V2 V1
-	 * cw2:  V0 R6 R5 R4 R3 R2 R1 R0
-	 *
-	 * R6:R0 = Reference Divider Word (RDW)
-	 * V8:V0 = VCO Divider Word (VDW)
-	 * S2:S0 = Output Divider Select (OD)
-	 * F1:F0 = Function of CLK2 Output
-	 * TTL = duty cycle
-	 * C1:C0 = internal load capacitance for cyrstal
-	 */
-
-	/* Adding 1 to get a "nicely" rounded number, but this needs
-	 * more tweaking to get a "properly" rounded number. */
-
-	freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD));
-
-	debug("ICS307: CW[0-2]: %02X %02X %02X => %lu Hz\n", cw0, cw1, cw2,
-			freq);
-	return freq;
-}
-
-unsigned long get_board_sys_clk(ulong dummy)
-{
-	return gd->bus_clk;
-}
-
-unsigned long get_board_ddr_clk(ulong dummy)
-{
-	return gd->mem_clk;
-}
-
-unsigned long calculate_board_sys_clk(ulong dummy)
-{
-	ulong val;
-
-	val = ics307_clk_freq(in_8(&pixis->sclk[0]), in_8(&pixis->sclk[1]),
-			      in_8(&pixis->sclk[2]));
-	debug("sysclk val = %lu\n", val);
-	return val;
-}
-
-unsigned long calculate_board_ddr_clk(ulong dummy)
-{
-	ulong val;
-
-	val = ics307_clk_freq(in_8(&pixis->dclk[0]), in_8(&pixis->dclk[1]),
-			      in_8(&pixis->dclk[2]));
-	debug("ddrclk val = %lu\n", val);
-	return val;
-}
-#else
-unsigned long get_board_sys_clk(ulong dummy)
-{
-	u8 i;
-	ulong val = 0;
-
-	i = in_8(&pixis->spd);
-	i &= 0x07;
-
-	switch (i) {
-		case 0:
-			val = 33333333;
-			break;
-		case 1:
-			val = 40000000;
-			break;
-		case 2:
-			val = 50000000;
-			break;
-		case 3:
-			val = 66666666;
-			break;
-		case 4:
-			val = 83333333;
-			break;
-		case 5:
-			val = 100000000;
-			break;
-		case 6:
-			val = 133333333;
-			break;
-		case 7:
-			val = 166666666;
-			break;
-	}
-
-	return val;
-}
-
-unsigned long get_board_ddr_clk(ulong dummy)
-{
-	u8 i;
-	ulong val = 0;
-
-	i = in_8(&pixis->spd);
-	i &= 0x38;
-	i >>= 3;
-
-	switch (i) {
-		case 0:
-			val = 33333333;
-			break;
-		case 1:
-			val = 40000000;
-			break;
-		case 2:
-			val = 50000000;
-			break;
-		case 3:
-			val = 66666666;
-			break;
-		case 4:
-			val = 83333333;
-			break;
-		case 5:
-			val = 100000000;
-			break;
-		case 6:
-			val = 133333333;
-			break;
-		case 7:
-			val = 166666666;
-			break;
-	}
-	return val;
-}
-#endif
-
 #ifdef CONFIG_TSEC_ENET
 int board_eth_init(bd_t *bis)
 {