powerpc: Remove T1024QDS_DDR4_SECURE_BOOT_defconfig board

DM_SPI and other driver model migration deadlines
are expired for this board.

Remove it.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>

1 files changed, 0 insertions, 328 deletions

diff --git a/board/freescale/t102xqds/README b/board/freescale/t102xqds/README
deleted file mode 100644
index c00e3bafbe..0000000000
--- a/board/freescale/t102xqds/README
+++ /dev/null
@@ -1,328 +0,0 @@
-T1024 SoC Overview
-------------------
-The T1024/T1023 dual core and T1014/T1013 single core QorIQ communication processor
-combines two or one 64-bit Power Architecture e5500 core respectively with high
-performance datapath acceleration logic, and network peripheral bus interfaces
-required for networking and telecommunications. This processor can be used in
-applications such as enterprise WLAN access points, routers, switches, firewall
-and other packet processing intensive small enterprise and branch office appliances,
-and general-purpose embedded computing. Its high level of integration offers
-significant performance benefits and greatly helps to simplify board design.
-
-
-The T1024 SoC includes the following function and features:
-- two e5500 cores, each with a private 256 KB L2 cache
-  - Up to 1.4 GHz with 64-bit ISA support (Power Architecture v2.06-compliant)
-  - Three levels of instructions: User, supervisor, and hypervisor
-  - Independent boot and reset
-  - Secure boot capability
-- 256 KB shared L3 CoreNet platform cache (CPC)
-- Interconnect CoreNet platform
-  - CoreNet coherency manager supporting coherent and noncoherent transactions
-    with prioritization and bandwidth allocation amongst CoreNet endpoints
-  - 150 Gbps coherent read bandwidth
-- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support
-- Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions:
-  - Packet parsing, classification, and distribution
-  - Queue management for scheduling, packet sequencing, and congestion management
-  - Cryptography Acceleration (SEC 5.x)
-  - IEEE 1588 support
-  - Hardware buffer management for buffer allocation and deallocation
-  - MACSEC on DPAA-based Ethernet ports
-- Ethernet interfaces
-  - Four 1 Gbps Ethernet controllers
-- Parallel Ethernet interfaces
-  - Two RGMII interfaces
-- High speed peripheral interfaces
-  - Three PCI Express 2.0 controllers/ports running at up to 5 GHz
-  - One SATA controller supporting 1.5 and 3.0 Gb/s operation
-  - One QSGMII interface
-  - Four SGMII interface supporting 1000 Mbps
-  - Three SGMII interfaces supporting up to 2500 Mbps
-  - 10GbE XFI or 10Base-KR interface
-- Additional peripheral interfaces
-  - Two USB 2.0 controllers with integrated PHY
-  - SD/eSDHC/eMMC
-  - eSPI controller
-  - Four I2C controllers
-  - Four UARTs
-  - Four GPIO controllers
-  - Integrated flash controller (IFC)
-  - LCD interface (DIU) with 12 bit dual data rate
-- Multicore programmable interrupt controller (PIC)
-- Two 8-channel DMA engines
-- Single source clocking implementation
-- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
-- QUICC Engine block
-  - 32-bit RISC controller for flexible support of the communications peripherals
-  - Serial DMA channel for receive and transmit on all serial channels
-  - Two universal communication controllers, supporting TDM, HDLC, and UART
-
-T1023 Personality
-------------------
-T1023 is a reduced personality of T1024 without QUICC Engine, DIU, and
-unavailable deep sleep. Rest of the blocks are almost same as T1024.
-Differences between T1024 and T1023
-Feature		T1024  T1023
-QUICC Engine:	yes    no
-DIU:		yes    no
-Deep Sleep:	yes    no
-I2C controller: 4      3
-DDR:		64-bit 32-bit
-IFC:		32-bit 28-bit
-
-
-T1024QDS board Overview
------------------------
-- SERDES Connections
-  4 lanes supporting the following:
-  - PCI Express: supports Gen 1 and Gen 2
-  - SGMII 1G and SGMII 2.5G
-  - QSGMII
-  - XFI
-  - SATA 2.0
-  - High-speed multiplexers route the SerDes traffic to appropriate slots or connectors.
-  - Aurora debug with dedicated connectors.
-- DDR Controller
-  - Supports up to 1600 MTPS data-rate.
-  - Supports one DDR4 or DDR3L module using DDR4 to DDR3L adapter card.
-    - Supports Single-, dual- or quad-rank DIMMs
-  - DDR power supplies 1.35V (DDR3L)/1.20V (DDR4) to all devices with automatic tracking of VTT.
-- IFC/Local Bus
-  - NAND Flash: 8-bit, async, up to 2GB
-  - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB
-    - NOR devices support 8 virtual banks
-    - Socketed to allow alternate devices
-  - GASIC: Simple (minimal) target within QIXIS FPGA
-  - PromJET rapid memory download support
-  - IFC Debug/Development card
-- Ethernet
-  - Two on-board RGMII 10M/100M/1G ethernet ports.
-  - One QSGMII interface
-  - Four SGMII interface supporting 1Gbps
-  - Three SGMII interfaces supporting 2.5Gbps
-  - one 10Gbps XFI or 10Base-KR interface
-- QIXIS System Logic FPGA
-  - Manages system power and reset sequencing.
-  - Manages the configurations of DUT, board, and clock for dynamic shmoo.
-  - Collects V-I-T data in background for code/power profiling.
-  - Supports legacy TMT test features (POSt, IRS, SYSCLK-synchronous assertion).
-  - General fault monitoring and logging.
-  - Powered from ATX 'standby' power supply that allows continuous operation while rest of the system is off.
-- Clocks
-  - System and DDR clock (SYSCLK, DDRCLK).
-    - Switch selectable to one of 16 common settings in the interval of 64 MHz-166 MHz.
-    - Software programmable in 1 MHz increments from 1-200 MHz.
-  - SERDES clocks
-    - Provides clocks to SerDes blocks and slots.
-    - 100 MHz, 125 MHz and 156.25 MHz options.
-    - Spread-spectrum option for 100 MHz.
-- Power Supplies
-  - Dedicated PMBus regulator for VDD and VDDC.
-  - Adjustable from 0.7V to 1.3V at 35A
-    - VDD can be disabled independanty from VDDC for “deep sleep”.
-    - DDR3L/DDR4 power supply for GVDD: 1.35 or 1.20V at up to 22A.
-    - VTT/MVREF automatically track operating voltage.
-    - Dedicated 2.5V VPP supply.
-  - Dedicated regulators/filters for AVDD supplies.
-  - Dedicated regulators for other supplies, for example OVDD, CVDD, DVDD, LVDD, POVDD, and EVDD.
-- Video
-  - DIU supports video up to 1280x1024x32 bpp.
-    - Chrontel CH7201 for HDMI connection.
-    - TI DS90C387R for direct LCD connection.
-    - Raw (not encoded) video connector for testing or other encoders.
-- USB
-  - Supports two USB 2.0 ports with integrated PHYs.
-    - Two type A ports with 5V@1.5A per port.
-    - Second port can be converted to OTG mini-AB.
-- SDHC
-  For T1024QDS, the SDHC port connects directly to an adapter card slot that has the following features:
-    - upport for optional clock feedback paths.
-    - Support for optional high-speed voltage translation direction controls.
-    - Support for SD slots for: SD, SDHC (1x, 4x, 8x) and MMC.
-    - Support for eMMC memory devices.
-- SPI
-  -On-board support of 3 different devices and sizes.
-- Other IO
-  - Two Serial ports
-  - ProfiBus port
-  - Four I2C ports
-
-
-Memory map on T1024QDS
-----------------------
-Start Address  End Address      Description			Size
-0xF_FFDF_0000  0xF_FFDF_0FFF    IFC - FPGA			4KB
-0xF_FF80_0000  0xF_FF80_FFFF    IFC - NAND Flash		64KB
-0xF_FE00_0000  0xF_FEFF_FFFF    CCSRBAR				16MB
-0xF_F802_0000  0xF_F802_FFFF    PCI Express 3 I/O Space		64KB
-0xF_F801_0000  0xF_F801_FFFF    PCI Express 2 I/O Space		64KB
-0xF_F800_0000  0xF_F800_FFFF    PCI Express 1 I/O Space		64KB
-0xF_F600_0000  0xF_F7FF_FFFF    Queue manager software portal   32MB
-0xF_F400_0000  0xF_F5FF_FFFF    Buffer manager software portal  32MB
-0xF_E800_0000  0xF_EFFF_FFFF    IFC - NOR Flash			128MB
-0xF_E000_0000  0xF_E7FF_FFFF    Promjet				128MB
-0xF_0000_0000  0xF_003F_FFFF    DCSR				4MB
-0xC_2000_0000  0xC_2FFF_FFFF    PCI Express 3 Mem Space		256MB
-0xC_1000_0000  0xC_1FFF_FFFF    PCI Express 2 Mem Space		256MB
-0xC_0000_0000  0xC_0FFF_FFFF    PCI Express 1 Mem Space		256MB
-0x0_0000_0000  0x0_ffff_ffff    DDR				4GB
-
-
-128MB NOR Flash memory Map
---------------------------
-Start Address   End Address     Definition			Max size
-0xEFF40000      0xEFFFFFFF      U-Boot (current bank)		768KB
-0xEFF20000      0xEFF3FFFF      U-Boot env (current bank)	128KB
-0xEFF00000      0xEFF1FFFF      FMAN Ucode (current bank)	128KB
-0xEFE00000      0xEFE3FFFF      QE firmware (current bank)	256KB
-0xED300000      0xEFEFFFFF      rootfs (alt bank)		44MB
-0xEC800000      0xEC8FFFFF      Hardware device tree (alt bank) 1MB
-0xEC020000      0xEC7FFFFF      Linux.uImage (alt bank)		7MB + 875KB
-0xEC000000      0xEC01FFFF      RCW (alt bank)			128KB
-0xEBF40000      0xEBFFFFFF      U-Boot (alt bank)		768KB
-0xEBF20000      0xEBF3FFFF      U-Boot env (alt bank)		128KB
-0xEBF00000      0xEBF1FFFF      FMAN ucode (alt bank)		128KB
-0xEBE00000      0xEBE3FFFF      QE firmware (alt bank)		256KB
-0xE9300000      0xEBEFFFFF      rootfs (current bank)		44MB
-0xE8800000      0xE88FFFFF      Hardware device tree (cur bank) 1MB
-0xE8020000      0xE86FFFFF      Linux.uImage (current bank)	7MB + 875KB
-0xE8000000      0xE801FFFF      RCW (current bank)		128KB
-
-
-SerDes clock vs DIP-switch settings
------------------------------------
-SRDS_PRTCL_S1	SD1_REF_CLK1	SD1_REF_CLK2	SW4[1:4]
-0x6F		100MHz		125MHz		1101
-0xD6		100MHz		100MHz		1111
-0x99		156.25MHz	100MHz		1011
-
-
-T1024 Clock frequency
-----------------------
-BIN   Core     DDR       Platform  FMan
-Bin1: 1400MHz  1600MT/s  400MHz    700MHz
-Bin2: 1200MHz  1600MT/s  400MHz    600MHz
-Bin3: 1000MHz  1600MT/s  400MHz    500MHz
-
-
-
-Software configurations and board settings
-------------------------------------------
-1. NOR boot:
-   a. build NOR boot image
-	$  make T1024QDS_defconfig    (For DDR3L, by default)
-	or make T1024QDS_D4_defconfig (For DDR4)
-	$  make
-   b. program u-boot.bin image to NOR flash
-	=> tftp 1000000 u-boot.bin
-	=> pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
-	set SW1[1:8] = '00010011', SW2[1] = '1', SW6[1:4] = '0000' for NOR boot
-
-   Switching between default bank0 and alternate bank4 on NOR flash
-   To change boot source to vbank4:
-	via software:   run command 'qixis_reset altbank' in U-Boot.
-	via DIP-switch: set SW6[1:4] = '0100'
-
-   To change boot source to vbank0:
-	via software:   run command 'qixis_reset' in U-Boot.
-	via DIP-Switch: set SW6[1:4] = '0000'
-
-2. NAND Boot:
-   a. build PBL image for NAND boot
-	$ make T1024QDS_NAND_defconfig
-	$ make
-   b. program u-boot-with-spl-pbl.bin to NAND flash
-	=> tftp 1000000 u-boot-with-spl-pbl.bin
-	=> nand erase 0 $filesize
-	=> nand write 1000000 0 $filesize
-	set SW1[1:8] = '10000010', SW2[1] = '0' and SW6[1:4] = '1001' for NAND boot
-
-3. SPI Boot:
-   a. build PBL image for SPI boot
-	$ make T1024QDS_SPIFLASH_defconfig
-	$ make
-   b. program u-boot-with-spl-pbl.bin to SPI flash
-	=> tftp 1000000 u-boot-with-spl-pbl.bin
-	=> sf probe 0
-	=> sf erase 0 f0000
-	=> sf write 1000000 0 $filesize
-	set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot
-
-4. SD Boot:
-   a. build PBL image for SD boot
-	$ make T1024QDS_SDCARD_defconfig
-	$ make
-   b. program u-boot-with-spl-pbl.bin to SD/MMC card
-	=> tftp 1000000 u-boot-with-spl-pbl.bin
-	=> mmc write 1000000 8 0x800
-	=> tftp 1000000 fsl_fman_ucode_t1024_xx.bin
-	=> mmc write 1000000 0x820 80
-	set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
-
-
-DIU/QE-TDM/SDXC settings
--------------------
-a) For TDM Riser:     set pin_mux=tdm in hwconfig
-b) For UCC(ProfiBus): set pin_mux=ucc in hwconfig
-c) For HDMI(DVI):     set pin_mux=hdmi in hwconfig
-d) For LCD(DFP):      set pin_mux=lcd in hwconfig
-e) For SDXC:	      set adaptor=sdxc in hwconfig
-
-2-stage NAND/SPI/SD boot loader
--------------------------------
-PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM.
-SPL further initializes DDR using SPD and environment variables
-and copy U-Boot(768 KB) from NAND/SPI/SD device to DDR.
-Finally SPL transers control to U-Boot for futher booting.
-
-SPL has following features:
- - Executes within 256K
- - No relocation required
-
-Run time view of SPL framework
--------------------------------------------------
-|Area		   | Address			|
--------------------------------------------------
-|SecureBoot header | 0xFFFC0000 (32KB)		|
--------------------------------------------------
-|GD, BD		   | 0xFFFC8000 (4KB)		|
--------------------------------------------------
-|ENV		   | 0xFFFC9000 (8KB)		|
--------------------------------------------------
-|HEAP		   | 0xFFFCB000 (30KB)		|
--------------------------------------------------
-|STACK		   | 0xFFFD8000 (22KB)		|
--------------------------------------------------
-|U-Boot SPL	   | 0xFFFD8000 (160KB)		|
--------------------------------------------------
-
-NAND Flash memory Map on T1024QDS
--------------------------------------------------------------
-Start		End		Definition	Size
-0x000000	0x0FFFFF	U-Boot		1MB
-0x100000	0x15FFFF	U-Boot env	8KB
-0x160000	0x17FFFF	FMAN Ucode	128KB
-0x180000	0x19FFFF	QE Firmware	128KB
-
-
-SD Card memory Map on T1024QDS
-----------------------------------------------------
-Block		#blocks		Definition	Size
-0x008		2048		U-Boot img	1MB
-0x800		0016		U-Boot env	8KB
-0x820		0256		FMAN Ucode	128KB
-0x920		0256		QE Firmware	128KB
-
-
-SPI Flash memory Map on T1024QDS
-----------------------------------------------------
-Start		End		Definition	Size
-0x000000	0x0FFFFF	U-Boot img	1MB
-0x100000	0x101FFF	U-Boot env	8KB
-0x110000	0x12FFFF	FMAN Ucode	128KB
-0x130000	0x14FFFF	QE Firmware	128KB
-
-
-For more details, please refer to T1024QDS Reference Manual and access
-website www.freescale.com and Freescale QorIQ SDK Infocenter document.