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authorYork Sun <york.sun@nxp.com>2017-12-05 10:57:54 -0800
committerYork Sun <york.sun@nxp.com>2017-12-06 14:54:12 -0800
commit316f0d0f8f3cbeeefda043e69f3e4e6aa57f7f1d (patch)
treee4201de6e106653a02a04c13f21cf3685bc878ee /board/freescale/t102xqds
parent0f2296bab1417faa5973e6d6690c8be0f83ecd08 (diff)
powerpc: mpc85xx: Fix static TLB table for SDRAM
Most predefined TLB tables don't have memory coherence bit set for SDRAM. This wasn't an issue before invalidate_dcache_range() function was enabled. Without the coherence bit, dcache invalidation doesn't automatically flush the cache. The coherence bit is already set when dynamic TLB table is used. For some boards with different SPL boot method, or with legacy fixed setting, this bit needs to be set in TLB files. Signed-off-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'board/freescale/t102xqds')
-rw-r--r--board/freescale/t102xqds/tlb.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/board/freescale/t102xqds/tlb.c b/board/freescale/t102xqds/tlb.c
index 409e173999..0d27a998c5 100644
--- a/board/freescale/t102xqds/tlb.c
+++ b/board/freescale/t102xqds/tlb.c
@@ -102,11 +102,11 @@ struct fsl_e_tlb_entry tlb_table[] = {
#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 12, BOOKE_PAGESZ_1G, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 13, BOOKE_PAGESZ_1G, 1)
#endif
/* entry 14 and 15 has been used hard coded, they will be disabled