diff options
| author | vijay rai <vijay.rai@freescale.com> | 2014-06-20 10:45:29 +0530 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-07-22 16:25:54 -0700 |
| commit | 6666017f44e39ec0385e3c7736b8c9af46cf4f08 (patch) | |
| tree | fab7529d9b9ac0b7f28fcbcd358c2ca52633311e /board/freescale/t1040qds/t1040qds_qixis.h | |
| parent | 591dd192307d81cf8f8705b06854e973c53d4c4d (diff) | |
powerpc/t1040qds: Initialize EPHY2 clock to RGMII only
Setting FPGA register brdcfg9 EPHY2 bits to '0' to initialize EPHY2 clock to RGMII mode.
Signed-off-by: Vijay Rai <vijay.rai@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board/freescale/t1040qds/t1040qds_qixis.h')
| -rw-r--r-- | board/freescale/t1040qds/t1040qds_qixis.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/board/freescale/t1040qds/t1040qds_qixis.h b/board/freescale/t1040qds/t1040qds_qixis.h index 98d2d39e6d..cef8ad0bfa 100644 --- a/board/freescale/t1040qds/t1040qds_qixis.h +++ b/board/freescale/t1040qds/t1040qds_qixis.h @@ -17,6 +17,10 @@ #define BRDCFG5_IMX_MASK 0xC0 #define BRDCFG5_IMX_DIU 0x80 +/* BRDCFG9[2] controls EPHY2 Clock */ +#define BRDCFG9_EPHY2_MASK 0x20 +#define BRDCFG9_EPHY2_VAL 0x00 + /* BRDCFG15[3] controls LCD Panel Powerdown*/ #define BRDCFG15_LCDPD_MASK 0x10 #define BRDCFG15_LCDPD_ENABLED 0x00 |