powerpc: Remove T1040QDS_DDR4_defconfig board

DM_SPI and other driver model migration deadlines
are expired for this board.

Remove it.

Patch-cc: Poonam Aggrwal <poonam.aggrwal@nxp.com>
Patch-cc: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>

16 files changed, 0 insertions, 1657 deletions

diff --git a/board/freescale/t1040qds/Kconfig b/board/freescale/t1040qds/Kconfig
deleted file mode 100644
index ec3ff0c1ec..0000000000
--- a/board/freescale/t1040qds/Kconfig
+++ /dev/null
@@ -1,14 +0,0 @@
-if TARGET_T1040QDS
-
-config SYS_BOARD
-	default "t1040qds"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "T1040QDS"
-
-source "board/freescale/common/Kconfig"
-
-endif
diff --git a/board/freescale/t1040qds/MAINTAINERS b/board/freescale/t1040qds/MAINTAINERS
deleted file mode 100644
index 1e276e3db9..0000000000
--- a/board/freescale/t1040qds/MAINTAINERS
+++ /dev/null
@@ -1,12 +0,0 @@
-T1040QDS BOARD
-M:	Poonam Aggrwal <poonam.aggrwal@nxp.com>
-S:	Maintained
-F:	board/freescale/t1040qds/
-F:	include/configs/T1040QDS.h
-F:	configs/T1040QDS_defconfig
-F:	configs/T1040QDS_DDR4_defconfig
-
-T1040QDS_SECURE_BOOT BOARD
-M:	Ruchika Gupta <ruchika.gupta@nxp.com>
-S:	Maintained
-F:	configs/T1040QDS_SECURE_BOOT_defconfig
diff --git a/board/freescale/t1040qds/Makefile b/board/freescale/t1040qds/Makefile
deleted file mode 100644
index e10a54af88..0000000000
--- a/board/freescale/t1040qds/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2013 Freescale Semiconductor, Inc.
-
-obj-y	+= t1040qds.o
-obj-y	+= ddr.o
-obj-$(CONFIG_PCI)     += pci.o
-obj-y	+= law.o
-obj-y	+= tlb.o
-obj-y	+= eth.o
-obj-y	+= diu.o
diff --git a/board/freescale/t1040qds/README b/board/freescale/t1040qds/README
deleted file mode 100644
index 6c5ffc07f8..0000000000
--- a/board/freescale/t1040qds/README
+++ /dev/null
@@ -1,169 +0,0 @@
-Overview
---------
-The T1040QDS is a Freescale reference board that hosts the T1040 SoC
-(and variants).
-
-T1040 SoC Overview
-------------------
-The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA
-processor cores with high-performance data path acceleration architecture
-and network peripheral interfaces required for networking & telecommunications.
-
-The T1040/T1042 SoC includes the following function and features:
-
- - Four e5500 cores, each with a private 256 KB L2 cache
- - 256 KB shared L3 CoreNet platform cache (CPC)
- - Interconnect CoreNet platform
- - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
-   support
- - Data Path Acceleration Architecture (DPAA) incorporating acceleration
- for the following functions:
-    -  Packet parsing, classification, and distribution
-    -  Queue management for scheduling, packet sequencing, and congestion
-    	management
-    -  Cryptography Acceleration (SEC 5.0)
-    - RegEx Pattern Matching Acceleration (PME 2.2)
-    - IEEE Std 1588 support
-    - Hardware buffer management for buffer allocation and deallocation
- - Ethernet interfaces
-    - Integrated 8-port Gigabit Ethernet switch (T1040 only)
-    - Four 1 Gbps Ethernet controllers
- - Two RGMII interfaces or one RGMII and one MII interfaces
- - High speed peripheral interfaces
-   - Four PCI Express 2.0 controllers running at up to 5 GHz
-   - Two SATA controllers supporting 1.5 and 3.0 Gb/s operation
-   - Upto two QSGMII interface
-   - Upto six SGMII interface supporting 1000 Mbps
-   - One SGMII interface supporting upto 2500 Mbps
- - Additional peripheral interfaces
-   - Two USB 2.0 controllers with integrated PHY
-   - SD/eSDHC/eMMC
-   -  eSPI controller
-   - Four I2C controllers
-   - Four UARTs
-   - Four GPIO controllers
-   - Integrated flash controller (IFC)
-   - LCD and HDMI interface (DIU) with 12 bit dual data rate
-   - TDM interface
- - Multicore programmable interrupt controller (PIC)
- - Two 8-channel DMA engines
- - Single source clocking implementation
- - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
-
- T1040QDS board Overview
- -----------------------
- - SERDES Connections, 8 lanes supporting:
-      — PCI Express: supporting Gen 1 and Gen 2;
-      — SGMII
-      — QSGMII
-      — SATA 2.0
-      — Aurora debug with dedicated connectors (T1040 only)
- - DDR Controller
-     - Supports rates of up to 1600 MHz data-rate
-     - Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types.
- -IFC/Local Bus
-     - NAND flash: 8-bit, async, up to 2GB.
-     - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB
-     - GASIC: Simple (minimal) target within Qixis FPGA
-     - PromJET rapid memory download support
- - Ethernet
-     - Two on-board RGMII 10/100/1G ethernet ports.
-     - PHY #0 remains powered up during deep-sleep (T1040 only)
- - QIXIS System Logic FPGA
- - Clocks
-     - System and DDR clock (SYSCLK, “DDRCLK”)
-     - SERDES clocks
- - Power Supplies
- - Video
-     - DIU supports video at up to 1280x1024x32bpp
- - USB
-     - Supports two USB 2.0 ports with integrated PHYs
-     — Two type A ports with 5V@1.5A per port.
-     — Second port can be converted to OTG mini-AB
- - SDHC
-     - SDHC port connects directly to an adapter card slot, featuring:
-     - Supporting SD slots for: SD, SDHC (1x, 4x, 8x) and/or MMC
-     — Supporting eMMC memory devices
- - SPI
-    -  On-board support of 3 different devices and sizes
- - Other IO
-    - Two Serial ports
-    - ProfiBus port
-    - Four I2C ports
-
-Memory map on T1040QDS
-----------------------
-The addresses in brackets are physical addresses.
-
-Start Address  End Address      Description                     Size
-0xF_FFDF_0000  0xF_FFDF_0FFF    IFC - FPGA                      4KB
-0xF_FF80_0000  0xF_FF80_FFFF    IFC - NAND Flash                64KB
-0xF_FE00_0000  0xF_FEFF_FFFF    CCSRBAR                         16MB
-0xF_F803_0000  0xF_F803_FFFF    PCI Express 4 I/O Space         64KB
-0xF_F802_0000  0xF_F802_FFFF    PCI Express 3 I/O Space	        64KB
-0xF_F801_0000  0xF_F801_FFFF    PCI Express 2 I/O Space         64KB
-0xF_F800_0000  0xF_F800_FFFF    PCI Express 1 I/O Space	        64KB
-0xF_F600_0000  0xF_F7FF_FFFF    Queue manager software portal   32MB
-0xF_F400_0000  0xF_F5FF_FFFF    Buffer manager software portal  32MB
-0xF_E800_0000  0xF_EFFF_FFFF    IFC - NOR Flash                 128MB
-0xF_E000_0000  0xF_E7FF_FFFF    Promjet                         128MB
-0xF_0000_0000  0xF_003F_FFFF    DCSR                            4MB
-0xC_3000_0000  0xC_3FFF_FFFF    PCI Express 4 Mem Space         256MB
-0xC_2000_0000  0xC_2FFF_FFFF    PCI Express 3 Mem Space         256MB
-0xC_1000_0000  0xC_1FFF_FFFF    PCI Express 2 Mem Space         256MB
-0xC_0000_0000  0xC_0FFF_FFFF    PCI Express 1 Mem Space         256MB
-0x0_0000_0000  0x0_ffff_ffff    DDR                             2GB
-
-
-NOR Flash memory Map on T1040QDS
---------------------------------
- Start          End             Definition                       Size
-0xEFF40000      0xEFFFFFFF      U-Boot (current bank)            768KB
-0xEFF20000      0xEFF3FFFF      U-Boot env (current bank)        128KB
-0xEFF00000      0xEFF1FFFF      FMAN Ucode (current bank)        128KB
-0xED300000      0xEFEFFFFF      rootfs (alt bank)                44MB
-0xEC800000      0xEC8FFFFF      Hardware device tree (alt bank)  1MB
-0xEC020000      0xEC7FFFFF      Linux.uImage (alt bank)          7MB + 875KB
-0xEC000000      0xEC01FFFF      RCW (alt bank)                   128KB
-0xEBF40000      0xEBFFFFFF      U-Boot (alt bank)                768KB
-0xEBF20000      0xEBF3FFFF      U-Boot env (alt bank)            128KB
-0xEBF00000      0xEBF1FFFF      FMAN ucode (alt bank)            128KB
-0xE9300000      0xEBEFFFFF      rootfs (current bank)            44MB
-0xE8800000      0xE88FFFFF      Hardware device tree (cur bank)  11MB + 512KB
-0xE8020000      0xE86FFFFF      Linux.uImage (current bank)      7MB + 875KB
-0xE8000000      0xE801FFFF      RCW (current bank)               128KB
-
-
-Various Software configurations/environment variables/commands
---------------------------------------------------------------
-The below commands apply to T1040QDS
-
-1. U-Boot environment variable hwconfig
-   The default hwconfig is:
-	hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;usb1:
-					dr_mode=host,phy_type=utmi
-   Note: For USB gadget set "dr_mode=peripheral"
-
-2. FMAN Ucode versions
-   fsl_fman_ucode_t1040.bin
-
-3. Switching to alternate bank
-   Commands for switching to alternate bank.
-
-	1. To change from vbank0 to vbank4
-		=> qixis_reset altbank (it will boot using vbank4)
-
-	2.To change from vbank4 to vbank0
-		=> qixis reset (it will boot using vbank0)
-
-T1040 Personality
---------------------
-
-T1022 Personality
---------------------
-T1022 is a reduced personality of T1040 with less core/clusters.
-
-T1042 Personality
---------------------
-T1042 is a reduced personality of T1040 without Integrated 8-port Gigabit
-Ethernet switch. Rest of the blocks are same as T1040
diff --git a/board/freescale/t1040qds/ddr.c b/board/freescale/t1040qds/ddr.c
deleted file mode 100644
index 0a817d0ee8..0000000000
--- a/board/freescale/t1040qds/ddr.c
+++ /dev/null
@@ -1,142 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013-2014 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <hwconfig.h>
-#include <init.h>
-#include <log.h>
-#include <asm/mmu.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include <asm/fsl_law.h>
-#include <asm/mpc85xx_gpio.h>
-#include <linux/delay.h>
-#include "ddr.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void fsl_ddr_board_options(memctl_options_t *popts,
-				dimm_params_t *pdimm,
-				unsigned int ctrl_num)
-{
-	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
-	ulong ddr_freq;
-
-	if (ctrl_num > 2) {
-		printf("Not supported controller number %d\n", ctrl_num);
-		return;
-	}
-	if (!pdimm->n_ranks)
-		return;
-
-	pbsp = udimms[0];
-
-	/* Get clk_adjust, cpo, write_data_delay,2t, according to the board ddr
-	 * freqency and n_banks specified in board_specific_parameters table.
-	 */
-	ddr_freq = get_ddr_freq(0) / 1000000;
-	while (pbsp->datarate_mhz_high) {
-		if (pbsp->n_ranks == pdimm->n_ranks &&
-		    (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
-			if (ddr_freq <= pbsp->datarate_mhz_high) {
-				popts->clk_adjust = pbsp->clk_adjust;
-				popts->wrlvl_start = pbsp->wrlvl_start;
-				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
-				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
-				goto found;
-			}
-			pbsp_highest = pbsp;
-		}
-		pbsp++;
-	}
-
-	if (pbsp_highest) {
-		printf("Error: board specific timing not found\n");
-		printf("for data rate %lu MT/s\n", ddr_freq);
-		printf("Trying to use the highest speed (%u) parameters\n",
-		       pbsp_highest->datarate_mhz_high);
-		popts->clk_adjust = pbsp_highest->clk_adjust;
-		popts->wrlvl_start = pbsp_highest->wrlvl_start;
-		popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
-		popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
-	} else {
-		panic("DIMM is not supported by this board");
-	}
-found:
-	debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
-		"\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
-		"wrlvl_ctrl_3 0x%x\n",
-		pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
-		pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
-		pbsp->wrlvl_ctl_3);
-
-	/*
-	 * Factors to consider for half-strength driver enable:
-	 *	- number of DIMMs installed
-	 */
-	popts->half_strength_driver_enable = 1;
-	/*
-	 * Write leveling override
-	 */
-	popts->wrlvl_override = 1;
-	popts->wrlvl_sample = 0xf;
-
-	/*
-	 * rtt and rtt_wr override
-	 */
-	popts->rtt_override = 0;
-
-	/* Enable ZQ calibration */
-	popts->zq_en = 1;
-
-	/* DHC_EN =1, ODT = 75 Ohm */
-#ifdef CONFIG_SYS_FSL_DDR4
-	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
-	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
-			  DDR_CDR2_VREF_OVRD(70);	/* Vref = 70% */
-
-	/* optimize cpo for erratum A-009942 */
-	popts->cpo_sample = 0x69;
-#else
-	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
-	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
-#endif
-}
-
-#if defined(CONFIG_DEEP_SLEEP)
-void board_mem_sleep_setup(void)
-{
-	void __iomem *qixis_base = (void *)QIXIS_BASE;
-
-	/* does not provide HW signals for power management */
-	clrbits_8(qixis_base + 0x21, 0x2);
-	/* Disable MCKE isolation */
-	gpio_set_value(2, 0);
-	udelay(1);
-}
-#endif
-
-int dram_init(void)
-{
-	phys_size_t dram_size;
-
-	puts("Initializing....using SPD\n");
-
-	dram_size = fsl_ddr_sdram();
-
-	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-	dram_size *= 0x100000;
-
-	puts("    DDR: ");
-
-#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
-	fsl_dp_resume();
-#endif
-
-	gd->ram_size = dram_size;
-
-	return 0;
-}
diff --git a/board/freescale/t1040qds/ddr.h b/board/freescale/t1040qds/ddr.h
deleted file mode 100644
index 0f88698ab5..0000000000
--- a/board/freescale/t1040qds/ddr.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2013-2014 Freescale Semiconductor, Inc.
- */
-
-#ifndef __DDR_H__
-#define __DDR_H__
-struct board_specific_parameters {
-	u32 n_ranks;
-	u32 datarate_mhz_high;
-	u32 rank_gb;
-	u32 clk_adjust;
-	u32 wrlvl_start;
-	u32 wrlvl_ctl_2;
-	u32 wrlvl_ctl_3;
-};
-
-/*
- * These tables contain all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- */
-
-static const struct board_specific_parameters udimm0[] = {
-	/*
-	 * memory controller 0
-	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl |
-	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |
-	 */
-#ifdef CONFIG_SYS_FSL_DDR4
-	{2,  1666, 0, 8,     7, 0x0808090B, 0x0C0D0E0A,},
-	{2,  1900, 0, 8,     6, 0x08080A0C, 0x0D0E0F0A,},
-	{1,  1666, 0, 8,     6, 0x0708090B, 0x0C0D0E09,},
-	{1,  1900, 0, 8,     6, 0x08080A0C, 0x0D0E0F0A,},
-	{1,  2200, 0, 8,     7, 0x08090A0D, 0x0F0F100C,},
-#elif defined(CONFIG_SYS_FSL_DDR3)
-	{2,  833,  0, 8,     6, 0x06060607, 0x08080807,},
-	{2,  1350, 0, 8,     7, 0x0708080A, 0x0A0B0C09,},
-	{2,  1666, 0, 8,     7, 0x0808090B, 0x0C0D0E0A,},
-	{1,  833,  0, 8,     6, 0x06060607, 0x08080807,},
-	{1,  1350, 0, 8,     7, 0x0708080A, 0x0A0B0C09,},
-	{1,  1666, 0, 8,     7, 0x0808090B, 0x0C0D0E0A,},
-#else
-#error DDR type not defined
-#endif
-	{}
-};
-
-static const struct board_specific_parameters *udimms[] = {
-	udimm0,
-};
-#endif
diff --git a/board/freescale/t1040qds/diu.c b/board/freescale/t1040qds/diu.c
deleted file mode 100644
index 0b1aeed69e..0000000000
--- a/board/freescale/t1040qds/diu.c
+++ /dev/null
@@ -1,98 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
- * Author: Priyanka Jain <Priyanka.Jain@freescale.com>
- */
-
-#include <common.h>
-#include <clock_legacy.h>
-#include <command.h>
-#include <linux/ctype.h>
-#include <asm/io.h>
-#include <stdio_dev.h>
-#include <video_fb.h>
-#include <fsl_diu_fb.h>
-#include "../common/qixis.h"
-#include "../common/diu_ch7301.h"
-#include "t1040qds.h"
-#include "t1040qds_qixis.h"
-
-/*
- * DIU Area Descriptor
- *
- * Note that we need to byte-swap the value before it's written to the AD
- * register.  So even though the registers don't look like they're in the same
- * bit positions as they are on the MPC8610, the same value is written to the
- * AD register on the MPC8610 and on the P1022.
- */
-#define AD_BYTE_F		0x10000000
-#define AD_ALPHA_C_SHIFT	25
-#define AD_BLUE_C_SHIFT		23
-#define AD_GREEN_C_SHIFT	21
-#define AD_RED_C_SHIFT		19
-#define AD_PIXEL_S_SHIFT	16
-#define AD_COMP_3_SHIFT		12
-#define AD_COMP_2_SHIFT		8
-#define AD_COMP_1_SHIFT		4
-#define AD_COMP_0_SHIFT		0
-
-void diu_set_pixel_clock(unsigned int pixclock)
-{
-	unsigned long speed_ccb, temp;
-	u32 pixval;
-	int ret = 0;
-	speed_ccb = get_bus_freq(0);
-	temp = 1000000000 / pixclock;
-	temp *= 1000;
-	pixval = speed_ccb / temp;
-
-	/* Program HDMI encoder */
-	/* Switch channel to DIU */
-	select_i2c_ch_pca9547(I2C_MUX_CH_DIU, 0);
-
-	/* Set dispaly encoder */
-	ret = diu_set_dvi_encoder(temp);
-	if (ret) {
-		puts("Failed to set DVI encoder\n");
-		return;
-	}
-
-	/* Switch channel to default */
-	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
-
-	/* Program pixel clock */
-	out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR,
-		 ((pixval << PXCK_BITS_START) & PXCK_MASK));
-	/* enable clock*/
-	out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, PXCKEN_MASK |
-		 ((pixval << PXCK_BITS_START) & PXCK_MASK));
-}
-
-int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
-{
-	u32 pixel_format;
-	u8 sw;
-
-	/*Route I2C4 to DIU system as HSYNC/VSYNC*/
-	sw = QIXIS_READ(brdcfg[5]);
-	QIXIS_WRITE(brdcfg[5],
-		    ((sw & ~(BRDCFG5_IMX_MASK)) | (BRDCFG5_IMX_DIU)));
-
-	/*Configure Display ouput port as HDMI*/
-	sw = QIXIS_READ(brdcfg[15]);
-	QIXIS_WRITE(brdcfg[15],
-		    ((sw & ~(BRDCFG15_LCDPD_MASK | BRDCFG15_DIUSEL_MASK))
-		      | (BRDCFG15_LCDPD_ENABLED | BRDCFG15_DIUSEL_HDMI)));
-
-	pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) |
-		(0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) |
-		(2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) |
-		(8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) |
-		(8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT));
-
-	printf("DIU:   Switching to monitor @ %ux%u\n",  xres, yres);
-
-
-	return fsl_diu_init(xres, yres, pixel_format, 0);
-}
diff --git a/board/freescale/t1040qds/eth.c b/board/freescale/t1040qds/eth.c
deleted file mode 100644
index b349b77951..0000000000
--- a/board/freescale/t1040qds/eth.c
+++ /dev/null
@@ -1,592 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-/*
- * The RGMII PHYs are provided by the two on-board PHY connected to
- * dTSEC instances 4 and 5. The SGMII PHYs are provided by one on-board
- * PHY or by the standard four-port SGMII riser card (VSC).
- */
-
-#include <common.h>
-#include <fdt_support.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/fsl_serdes.h>
-#include <asm/immap_85xx.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <malloc.h>
-#include <fsl_dtsec.h>
-#include <vsc9953.h>
-
-#include "../common/fman.h"
-#include "../common/qixis.h"
-
-#include "t1040qds_qixis.h"
-
-#ifdef CONFIG_FMAN_ENET
- /* - In T1040 there are only 8 SERDES lanes, spread across 2 SERDES banks.
- *   Bank 1 -> Lanes A, B, C, D
- *   Bank 2 -> Lanes E, F, G, H
- */
-
- /* Mapping of 8 SERDES lanes to T1040 QDS board slots. A value of '0' here
-  * means that the mapping must be determined dynamically, or that the lane
-  * maps to something other than a board slot.
-  */
-static u8 lane_to_slot[] = {
-	0, 0, 0, 0, 0, 0, 0, 0
-};
-
-/* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs
- * housed.
- */
-static int riser_phy_addr[] = {
-	CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR,
-	CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR,
-	CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR,
-	CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR,
-};
-
-/* Slot2 does not have EMI connections */
-#define EMI_NONE	0xFFFFFFFF
-#define EMI1_RGMII0	0
-#define EMI1_RGMII1	1
-#define EMI1_SLOT1	2
-#define EMI1_SLOT3	3
-#define EMI1_SLOT4	4
-#define EMI1_SLOT5	5
-#define EMI1_SLOT6	6
-#define EMI1_SLOT7	7
-#define EMI2		8
-
-static int mdio_mux[NUM_FM_PORTS];
-
-static const char * const mdio_names[] = {
-	"T1040_QDS_MDIO0",
-	"T1040_QDS_MDIO1",
-	"T1040_QDS_MDIO2",
-	"T1040_QDS_MDIO3",
-	"T1040_QDS_MDIO4",
-	"T1040_QDS_MDIO5",
-	"T1040_QDS_MDIO6",
-	"T1040_QDS_MDIO7",
-};
-
-struct t1040_qds_mdio {
-	u8 muxval;
-	struct mii_dev *realbus;
-};
-
-static const char *t1040_qds_mdio_name_for_muxval(u8 muxval)
-{
-	return mdio_names[muxval];
-}
-
-struct mii_dev *mii_dev_for_muxval(u8 muxval)
-{
-	struct mii_dev *bus;
-	const char *name = t1040_qds_mdio_name_for_muxval(muxval);
-
-	if (!name) {
-		printf("No bus for muxval %x\n", muxval);
-		return NULL;
-	}
-
-	bus = miiphy_get_dev_by_name(name);
-
-	if (!bus) {
-		printf("No bus by name %s\n", name);
-		return NULL;
-	}
-
-	return bus;
-}
-
-static void t1040_qds_mux_mdio(u8 muxval)
-{
-	u8 brdcfg4;
-	if (muxval <= 7) {
-		brdcfg4 = QIXIS_READ(brdcfg[4]);
-		brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
-		brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
-		QIXIS_WRITE(brdcfg[4], brdcfg4);
-	}
-}
-
-static int t1040_qds_mdio_read(struct mii_dev *bus, int addr, int devad,
-				int regnum)
-{
-	struct t1040_qds_mdio *priv = bus->priv;
-
-	t1040_qds_mux_mdio(priv->muxval);
-
-	return priv->realbus->read(priv->realbus, addr, devad, regnum);
-}
-
-static int t1040_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
-				int regnum, u16 value)
-{
-	struct t1040_qds_mdio *priv = bus->priv;
-
-	t1040_qds_mux_mdio(priv->muxval);
-
-	return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
-}
-
-static int t1040_qds_mdio_reset(struct mii_dev *bus)
-{
-	struct t1040_qds_mdio *priv = bus->priv;
-
-	return priv->realbus->reset(priv->realbus);
-}
-
-static int t1040_qds_mdio_init(char *realbusname, u8 muxval)
-{
-	struct t1040_qds_mdio *pmdio;
-	struct mii_dev *bus = mdio_alloc();
-
-	if (!bus) {
-		printf("Failed to allocate t1040_qds MDIO bus\n");
-		return -1;
-	}
-
-	pmdio = malloc(sizeof(*pmdio));
-	if (!pmdio) {
-		printf("Failed to allocate t1040_qds private data\n");
-		free(bus);
-		return -1;
-	}
-
-	bus->read = t1040_qds_mdio_read;
-	bus->write = t1040_qds_mdio_write;
-	bus->reset = t1040_qds_mdio_reset;
-	strcpy(bus->name, t1040_qds_mdio_name_for_muxval(muxval));
-
-	pmdio->realbus = miiphy_get_dev_by_name(realbusname);
-
-	if (!pmdio->realbus) {
-		printf("No bus with name %s\n", realbusname);
-		free(bus);
-		free(pmdio);
-		return -1;
-	}
-
-	pmdio->muxval = muxval;
-	bus->priv = pmdio;
-
-	return mdio_register(bus);
-}
-
-/*
- * Initialize the lane_to_slot[] array.
- *
- * On the T1040QDS board the mapping is controlled by ?? register.
- */
-static void initialize_lane_to_slot(void)
-{
-	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-	int serdes1_prtcl = (in_be32(&gur->rcwsr[4]) &
-				FSL_CORENET2_RCWSR4_SRDS1_PRTCL)
-		>> FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
-
-	QIXIS_WRITE(cms[0], 0x07);
-
-	switch (serdes1_prtcl) {
-	case 0x60:
-	case 0x66:
-	case 0x67:
-	case 0x69:
-		lane_to_slot[1] = 7;
-		lane_to_slot[2] = 6;
-		lane_to_slot[3] = 5;
-		break;
-	case 0x86:
-		lane_to_slot[1] = 7;
-		lane_to_slot[2] = 7;
-		lane_to_slot[3] = 7;
-		break;
-	case 0x87:
-		lane_to_slot[1] = 7;
-		lane_to_slot[2] = 7;
-		lane_to_slot[3] = 7;
-		lane_to_slot[7] = 7;
-		break;
-	case 0x89:
-		lane_to_slot[1] = 7;
-		lane_to_slot[2] = 7;
-		lane_to_slot[3] = 7;
-		lane_to_slot[6] = 7;
-		lane_to_slot[7] = 7;
-		break;
-	case 0x8d:
-		lane_to_slot[1] = 7;
-		lane_to_slot[2] = 7;
-		lane_to_slot[3] = 7;
-		lane_to_slot[5] = 3;
-		lane_to_slot[6] = 3;
-		lane_to_slot[7] = 3;
-		break;
-	case 0x8F:
-	case 0x85:
-		lane_to_slot[1] = 7;
-		lane_to_slot[2] = 6;
-		lane_to_slot[3] = 5;
-		lane_to_slot[6] = 3;
-		lane_to_slot[7] = 3;
-		break;
-	case 0xA5:
-		lane_to_slot[1] = 7;
-		lane_to_slot[6] = 3;
-		lane_to_slot[7] = 3;
-		break;
-	case 0xA7:
-		lane_to_slot[1] = 7;
-		lane_to_slot[2] = 6;
-		lane_to_slot[3] = 5;
-		lane_to_slot[7] = 7;
-		break;
-	case 0xAA:
-		lane_to_slot[1] = 7;
-		lane_to_slot[6] = 7;
-		lane_to_slot[7] = 7;
-		break;
-	case 0x40:
-		lane_to_slot[2] = 7;
-		lane_to_slot[3] = 7;
-		break;
-	default:
-		printf("qds: Fman: Unsupported SerDes Protocol 0x%02x\n",
-		       serdes1_prtcl);
-		break;
-	}
-}
-
-/*
- * Given the following ...
- *
- * 1) A pointer to an Fman Ethernet node (as identified by the 'compat'
- * compatible string and 'addr' physical address)
- *
- * 2) An Fman port
- *
- * ... update the phy-handle property of the Ethernet node to point to the
- * right PHY. This assumes that we already know the PHY for each port.
- *
- * The offset of the Fman Ethernet node is also passed in for convenience, but
- * it is not used, and we recalculate the offset anyway.
- *
- * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC.
- * Inside the Fman, "ports" are things that connect to MACs. We only call them
- * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs
- * and ports are the same thing.
- *
- */
-void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
-			      enum fm_port port, int offset)
-{
-	phy_interface_t intf = fm_info_get_enet_if(port);
-	char phy[16];
-
-	/* The RGMII PHY is identified by the MAC connected to it */
-	if (intf == PHY_INTERFACE_MODE_RGMII) {
-		sprintf(phy, "rgmii_phy%u", port == FM1_DTSEC4 ? 1 : 2);
-		fdt_set_phy_handle(fdt, compat, addr, phy);
-	}
-
-	/* The SGMII PHY is identified by the MAC connected to it */
-	if (intf == PHY_INTERFACE_MODE_SGMII) {
-		int lane = serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1
-						 + port);
-		u8 slot;
-		if (lane < 0)
-			return;
-		slot = lane_to_slot[lane];
-		if (slot) {
-			/* Slot housing a SGMII riser card */
-			sprintf(phy, "phy_s%x_%02x", slot,
-				(fm_info_get_phy_address(port - FM1_DTSEC1)-
-				CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR + 1));
-			fdt_set_phy_handle(fdt, compat, addr, phy);
-		}
-	}
-}
-
-void fdt_fixup_board_enet(void *fdt)
-{
-	int i, lane, idx;
-
-	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
-		idx = i - FM1_DTSEC1;
-		switch (fm_info_get_enet_if(i)) {
-		case PHY_INTERFACE_MODE_SGMII:
-			lane = serdes_get_first_lane(FSL_SRDS_1,
-						     SGMII_FM1_DTSEC1 + idx);
-			if (lane < 0)
-				break;
-
-			switch (mdio_mux[i]) {
-			case EMI1_SLOT3:
-				fdt_status_okay_by_alias(fdt, "emi1_slot3");
-				break;
-			case EMI1_SLOT5:
-				fdt_status_okay_by_alias(fdt, "emi1_slot5");
-				break;
-			case EMI1_SLOT6:
-				fdt_status_okay_by_alias(fdt, "emi1_slot6");
-				break;
-			case EMI1_SLOT7:
-				fdt_status_okay_by_alias(fdt, "emi1_slot7");
-				break;
-			}
-		break;
-		case PHY_INTERFACE_MODE_RGMII:
-			if (i == FM1_DTSEC4)
-				fdt_status_okay_by_alias(fdt, "emi1_rgmii0");
-
-			if (i == FM1_DTSEC5)
-				fdt_status_okay_by_alias(fdt, "emi1_rgmii1");
-			break;
-		default:
-			break;
-		}
-	}
-}
-#endif /* #ifdef CONFIG_FMAN_ENET */
-
-static void set_brdcfg9_for_gtx_clk(void)
-{
-	u8 brdcfg9;
-	brdcfg9 = QIXIS_READ(brdcfg[9]);
-/* Initializing EPHY2 clock to RGMII mode */
-	brdcfg9 &= ~(BRDCFG9_EPHY2_MASK);
-	brdcfg9 |= (BRDCFG9_EPHY2_VAL);
-	QIXIS_WRITE(brdcfg[9], brdcfg9);
-}
-
-void t1040_handle_phy_interface_sgmii(int i)
-{
-	int lane, idx, slot;
-	idx = i - FM1_DTSEC1;
-	lane = serdes_get_first_lane(FSL_SRDS_1,
-			SGMII_FM1_DTSEC1 + idx);
-
-	if (lane < 0)
-		return;
-	slot = lane_to_slot[lane];
-
-	switch (slot) {
-	case 1:
-		mdio_mux[i] = EMI1_SLOT1;
-		fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
-		break;
-	case 3:
-		if (FM1_DTSEC4 == i)
-			fm_info_set_phy_address(i, riser_phy_addr[0]);
-		if (FM1_DTSEC5 == i)
-			fm_info_set_phy_address(i, riser_phy_addr[1]);
-
-		mdio_mux[i] = EMI1_SLOT3;
-
-		fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
-		break;
-	case 4:
-		mdio_mux[i] = EMI1_SLOT4;
-		fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
-		break;
-	case 5:
-		/* Slot housing a SGMII riser card? */
-		fm_info_set_phy_address(i, riser_phy_addr[0]);
-		mdio_mux[i] = EMI1_SLOT5;
-		fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
-		break;
-	case 6:
-		/* Slot housing a SGMII riser card? */
-		fm_info_set_phy_address(i, riser_phy_addr[0]);
-		mdio_mux[i] = EMI1_SLOT6;
-		fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
-		break;
-	case 7:
-		if (FM1_DTSEC1 == i)
-			fm_info_set_phy_address(i, riser_phy_addr[0]);
-		if (FM1_DTSEC2 == i)
-			fm_info_set_phy_address(i, riser_phy_addr[1]);
-		if (FM1_DTSEC3 == i)
-			fm_info_set_phy_address(i, riser_phy_addr[2]);
-		if (FM1_DTSEC5 == i)
-			fm_info_set_phy_address(i, riser_phy_addr[3]);
-
-		mdio_mux[i] = EMI1_SLOT7;
-		fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
-		break;
-	default:
-		break;
-	}
-	fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
-}
-void t1040_handle_phy_interface_rgmii(int i)
-{
-	fm_info_set_phy_address(i, i == FM1_DTSEC5 ?
-			CONFIG_SYS_FM1_DTSEC5_PHY_ADDR :
-			CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
-	mdio_mux[i] = (i == FM1_DTSEC5) ? EMI1_RGMII1 :
-		EMI1_RGMII0;
-	fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
-}
-
-int board_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_FMAN_ENET
-	struct memac_mdio_info memac_mdio_info;
-	unsigned int i;
-#ifdef CONFIG_VSC9953
-	int lane;
-	int phy_addr;
-	phy_interface_t phy_int;
-	struct mii_dev *bus;
-#endif
-
-	printf("Initializing Fman\n");
-	set_brdcfg9_for_gtx_clk();
-
-	initialize_lane_to_slot();
-
-	/* Initialize the mdio_mux array so we can recognize empty elements */
-	for (i = 0; i < NUM_FM_PORTS; i++)
-		mdio_mux[i] = EMI_NONE;
-
-	memac_mdio_info.regs =
-		(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
-	memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
-	/* Register the real 1G MDIO bus */
-	fm_memac_mdio_init(bis, &memac_mdio_info);
-
-	/* Register the muxing front-ends to the MDIO buses */
-	t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII0);
-	t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
-	t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
-	t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
-	t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
-	t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
-	t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6);
-	t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
-
-	/*
-	 * Program on board RGMII PHY addresses. If the SGMII Riser
-	 * card used, we'll override the PHY address later. For any DTSEC that
-	 * is RGMII, we'll also override its PHY address later. We assume that
-	 * DTSEC4 and DTSEC5 are used for RGMII.
-	 */
-	fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
-	fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
-
-	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
-		switch (fm_info_get_enet_if(i)) {
-		case PHY_INTERFACE_MODE_QSGMII:
-			fm_info_set_mdio(i, NULL);
-			break;
-		case PHY_INTERFACE_MODE_SGMII:
-			t1040_handle_phy_interface_sgmii(i);
-			break;
-
-		case PHY_INTERFACE_MODE_RGMII:
-			/* Only DTSEC4 and DTSEC5 can be routed to RGMII */
-			t1040_handle_phy_interface_rgmii(i);
-			break;
-		default:
-			break;
-		}
-	}
-
-#ifdef CONFIG_VSC9953
-	for (i = 0; i < VSC9953_MAX_PORTS; i++) {
-		lane = -1;
-		phy_addr = 0;
-		phy_int = PHY_INTERFACE_MODE_NONE;
-		switch (i) {
-		case 0:
-		case 1:
-		case 2:
-		case 3:
-			lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_A);
-			/* PHYs connected over QSGMII */
-			if (lane >= 0) {
-				phy_addr = CONFIG_SYS_FM1_QSGMII21_PHY_ADDR +
-						i;
-				phy_int = PHY_INTERFACE_MODE_QSGMII;
-				break;
-			}
-			lane = serdes_get_first_lane(FSL_SRDS_1,
-					SGMII_SW1_MAC1 + i);
-
-			if (lane < 0)
-				break;
-
-			/* PHYs connected over QSGMII */
-			if (i != 3 || lane_to_slot[lane] == 7)
-				phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR
-					+ i;
-			else
-				phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR;
-			phy_int = PHY_INTERFACE_MODE_SGMII;
-			break;
-		case 4:
-		case 5:
-		case 6:
-		case 7:
-			lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_B);
-			/* PHYs connected over QSGMII */
-			if (lane >= 0) {
-				phy_addr = CONFIG_SYS_FM1_QSGMII11_PHY_ADDR +
-						i - 4;
-				phy_int = PHY_INTERFACE_MODE_QSGMII;
-				break;
-			}
-			lane = serdes_get_first_lane(FSL_SRDS_1,
-					SGMII_SW1_MAC1 + i);
-			/* PHYs connected over SGMII */
-			if (lane >= 0) {
-				phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR
-						+ i - 3;
-				phy_int = PHY_INTERFACE_MODE_SGMII;
-			}
-			break;
-		case 8:
-			if (serdes_get_first_lane(FSL_SRDS_1,
-						  SGMII_FM1_DTSEC1) < 0)
-				/* FM1@DTSEC1 is connected to SW1@PORT8 */
-				vsc9953_port_enable(i);
-			break;
-		case 9:
-			if (serdes_get_first_lane(FSL_SRDS_1,
-						  SGMII_FM1_DTSEC2) < 0) {
-				/* Enable L2 On MAC2 using SCFG */
-				struct ccsr_scfg *scfg = (struct ccsr_scfg *)
-						CONFIG_SYS_MPC85xx_SCFG;
-
-				out_be32(&scfg->esgmiiselcr,
-					 in_be32(&scfg->esgmiiselcr) |
-					 (0x80000000));
-				vsc9953_port_enable(i);
-			}
-			break;
-		}
-
-		if (lane >= 0) {
-			bus = mii_dev_for_muxval(lane_to_slot[lane]);
-			vsc9953_port_info_set_mdio(i, bus);
-			vsc9953_port_enable(i);
-		}
-		vsc9953_port_info_set_phy_address(i, phy_addr);
-		vsc9953_port_info_set_phy_int(i, phy_int);
-	}
-
-#endif
-	cpu_eth_init(bis);
-#endif
-
-	return pci_eth_init(bis);
-}
diff --git a/board/freescale/t1040qds/law.c b/board/freescale/t1040qds/law.c
deleted file mode 100644
index cf27655c14..0000000000
--- a/board/freescale/t1040qds/law.c
+++ /dev/null
@@ -1,31 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
-#ifdef CONFIG_MTD_NOR_FLASH
-	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
-#endif
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
-	SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
-#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
-	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
-#endif
-#ifdef QIXIS_BASE_PHYS
-	SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
-#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
-	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
-#endif
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
-	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
-#endif
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/t1040qds/pci.c b/board/freescale/t1040qds/pci.c
deleted file mode 100644
index 5152cdf18a..0000000000
--- a/board/freescale/t1040qds/pci.c
+++ /dev/null
@@ -1,23 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <pci.h>
-#include <asm/fsl_pci.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <asm/fsl_serdes.h>
-
-void pci_init_board(void)
-{
-	fsl_pcie_init_board(0);
-}
-
-void pci_of_setup(void *blob, bd_t *bd)
-{
-	FT_FSL_PCI_SETUP;
-}
diff --git a/board/freescale/t1040qds/t1040_pbi.cfg b/board/freescale/t1040qds/t1040_pbi.cfg
deleted file mode 100644
index 121b005baf..0000000000
--- a/board/freescale/t1040qds/t1040_pbi.cfg
+++ /dev/null
@@ -1,27 +0,0 @@
-#PBI commands
-#Initialize CPC1
-09010000 00200400
-09138000 00000000
-091380c0 00000100
-#Configure CPC1 as 256KB SRAM
-09010100 00000000
-09010104 fffc0007
-09010f00 081e000d
-09010000 80000000
-#Configure LAW for CPC1
-09000cf0 00000000
-09000cf4 fffc0000
-09000cf8 81000011
-#Configure alternate space
-09000010 00000000
-09000014 ff000000
-09000018 81000000
-#Configure SPI controller
-09110000 80000403
-09110020 2d170008
-09110024 00100008
-09110028 00100008
-0911002c 00100008
-#Flush PBL data
-09138000 00000000
-091380c0 00000000
diff --git a/board/freescale/t1040qds/t1040_rcw.cfg b/board/freescale/t1040qds/t1040_rcw.cfg
deleted file mode 100644
index 0d0dfa5a46..0000000000
--- a/board/freescale/t1040qds/t1040_rcw.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-# serdes protocol 0x66
-0a10000c 0c000000 00000000 00000000
-66000002 00000000 fc027000 01000000
-00000000 00000000 00000000 00030810
-00000000 03fc500f 00000000 00000000
diff --git a/board/freescale/t1040qds/t1040qds.c b/board/freescale/t1040qds/t1040qds.c
deleted file mode 100644
index cf38d843ac..0000000000
--- a/board/freescale/t1040qds/t1040qds.c
+++ /dev/null
@@ -1,307 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <fdt_support.h>
-#include <i2c.h>
-#include <image.h>
-#include <init.h>
-#include <netdev.h>
-#include <linux/compiler.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_liodn.h>
-#include <fm_eth.h>
-#include <hwconfig.h>
-
-#include "../common/sleep.h"
-#include "../common/qixis.h"
-#include "t1040qds.h"
-#include "t1040qds_qixis.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	char buf[64];
-	u8 sw;
-	struct cpu_type *cpu = gd->arch.cpu;
-	static const char *const freq[] = {"100", "125", "156.25", "161.13",
-						"122.88", "122.88", "122.88"};
-	int clock;
-
-	printf("Board: %sQDS, ", cpu->name);
-	printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
-	       QIXIS_READ(id), QIXIS_READ(arch));
-
-	sw = QIXIS_READ(brdcfg[0]);
-	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
-
-	if (sw < 0x8)
-		printf("vBank: %d\n", sw);
-	else if (sw == 0x8)
-		puts("PromJet\n");
-	else if (sw == 0x9)
-		puts("NAND\n");
-	else if (sw == 0x15)
-		printf("IFCCard\n");
-	else
-		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
-
-	printf("FPGA: v%d (%s), build %d",
-	       (int)QIXIS_READ(scver), qixis_read_tag(buf),
-	       (int)qixis_read_minor());
-	/* the timestamp string contains "\n" at the end */
-	printf(" on %s", qixis_read_time(buf));
-
-	/*
-	 * Display the actual SERDES reference clocks as configured by the
-	 * dip switches on the board.  Note that the SWx registers could
-	 * technically be set to force the reference clocks to match the
-	 * values that the SERDES expects (or vice versa).  For now, however,
-	 * we just display both values and hope the user notices when they
-	 * don't match.
-	 */
-	puts("SERDES Reference: ");
-	sw = QIXIS_READ(brdcfg[2]);
-	clock = (sw >> 6) & 3;
-	printf("Clock1=%sMHz ", freq[clock]);
-	clock = (sw >> 4) & 3;
-	printf("Clock2=%sMHz\n", freq[clock]);
-
-	return 0;
-}
-
-int select_i2c_ch_pca9547(u8 ch, int bus_num)
-{
-	int ret;
-
-#ifdef CONFIG_DM_I2C
-	struct udevice *dev;
-
-	ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
-	if (ret) {
-		printf("%s: Cannot find udev for a bus %d\n", __func__,
-		       bus_num);
-		return ret;
-	}
-
-	ret = dm_i2c_write(dev, 0, &ch, 1);
-#else
-	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
-#endif
-	if (ret) {
-		puts("PCA: failed to select proper channel\n");
-		return ret;
-	}
-
-	return 0;
-}
-
-static void qe_board_setup(void)
-{
-	u8 brdcfg15, brdcfg9;
-
-	if (hwconfig("qe") && hwconfig("tdm")) {
-		brdcfg15 = QIXIS_READ(brdcfg[15]);
-		/*
-		 * TDMRiser uses QE-TDM
-		 * Route QE_TDM signals to TDM Riser slot
-		 */
-		QIXIS_WRITE(brdcfg[15], brdcfg15 | 7);
-	} else if (hwconfig("qe") && hwconfig("uart")) {
-		brdcfg15 = QIXIS_READ(brdcfg[15]);
-		brdcfg9 = QIXIS_READ(brdcfg[9]);
-		/*
-		 * Route QE_TDM signals to UCC
-		 * ProfiBus controlled by UCC3
-		 */
-		brdcfg15 &= 0xfc;
-		QIXIS_WRITE(brdcfg[15], brdcfg15 | 2);
-		QIXIS_WRITE(brdcfg[9], brdcfg9 | 4);
-	}
-}
-
-int board_early_init_f(void)
-{
-#if defined(CONFIG_DEEP_SLEEP)
-	if (is_warm_boot())
-		fsl_dp_disable_console();
-#endif
-
-	return 0;
-}
-
-int board_early_init_r(void)
-{
-#ifdef CONFIG_SYS_FLASH_BASE
-	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
-	int flash_esel = find_tlb_idx((void *)flashbase, 1);
-
-	/*
-	 * Remap Boot flash + PROMJET region to caching-inhibited
-	 * so that flash can be erased properly.
-	 */
-
-	/* Flush d-cache and invalidate i-cache of any FLASH data */
-	flush_dcache();
-	invalidate_icache();
-
-	if (flash_esel == -1) {
-		/* very unlikely unless something is messed up */
-		puts("Error: Could not find TLB for FLASH BASE\n");
-		flash_esel = 2;	/* give our best effort to continue */
-	} else {
-		/* invalidate existing TLB entry for flash + promjet */
-		disable_tlb(flash_esel);
-	}
-
-	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
-		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, flash_esel, BOOKE_PAGESZ_256M, 1);
-#endif
-	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
-
-	return 0;
-}
-
-unsigned long get_board_sys_clk(void)
-{
-	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
-
-	switch (sysclk_conf & 0x0F) {
-	case QIXIS_SYSCLK_64:
-		return 64000000;
-	case QIXIS_SYSCLK_83:
-		return 83333333;
-	case QIXIS_SYSCLK_100:
-		return 100000000;
-	case QIXIS_SYSCLK_125:
-		return 125000000;
-	case QIXIS_SYSCLK_133:
-		return 133333333;
-	case QIXIS_SYSCLK_150:
-		return 150000000;
-	case QIXIS_SYSCLK_160:
-		return 160000000;
-	case QIXIS_SYSCLK_166:
-		return 166666666;
-	}
-	return 66666666;
-}
-
-unsigned long get_board_ddr_clk(void)
-{
-	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
-
-	switch ((ddrclk_conf & 0x30) >> 4) {
-	case QIXIS_DDRCLK_100:
-		return 100000000;
-	case QIXIS_DDRCLK_125:
-		return 125000000;
-	case QIXIS_DDRCLK_133:
-		return 133333333;
-	}
-	return 66666666;
-}
-
-#define NUM_SRDS_BANKS	2
-int misc_init_r(void)
-{
-	u8 sw;
-	serdes_corenet_t *srds_regs =
-		(void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
-	u32 actual[NUM_SRDS_BANKS] = { 0 };
-	int i;
-
-	sw = QIXIS_READ(brdcfg[2]);
-	for (i = 0; i < NUM_SRDS_BANKS; i++) {
-		unsigned int clock = (sw >> (6 - 2 * i)) & 3;
-		switch (clock) {
-		case 0:
-			actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
-			break;
-		case 1:
-			actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
-			break;
-		case 2:
-			actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
-			break;
-		}
-	}
-
-	puts("SerDes1");
-	for (i = 0; i < NUM_SRDS_BANKS; i++) {
-		u32 pllcr0 = srds_regs->bank[i].pllcr0;
-		u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
-		if (expected != actual[i]) {
-			printf("expects ref clk%d %sMHz, but actual is %sMHz\n",
-			       i + 1, serdes_clock_to_string(expected),
-			       serdes_clock_to_string(actual[i]));
-		}
-	}
-
-	qe_board_setup();
-
-	return 0;
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	phys_addr_t base;
-	phys_size_t size;
-
-	ft_cpu_setup(blob, bd);
-
-	base = env_get_bootm_low();
-	size = env_get_bootm_size();
-
-	fdt_fixup_memory(blob, (u64)base, (u64)size);
-
-#ifdef CONFIG_PCI
-	pci_of_setup(blob, bd);
-#endif
-
-	fdt_fixup_liodn(blob);
-
-#ifdef CONFIG_HAS_FSL_DR_USB
-	fsl_fdt_fixup_dr_usb(blob, bd);
-#endif
-
-#ifdef CONFIG_SYS_DPAA_FMAN
-#ifndef CONFIG_DM_ETH
-	fdt_fixup_fman_ethernet(blob);
-#endif
-	fdt_fixup_board_enet(blob);
-#endif
-
-	return 0;
-}
-
-void qixis_dump_switch(void)
-{
-	int i, nr_of_cfgsw;
-
-	QIXIS_WRITE(cms[0], 0x00);
-	nr_of_cfgsw = QIXIS_READ(cms[1]);
-
-	puts("DIP switch settings dump:\n");
-	for (i = 1; i <= nr_of_cfgsw; i++) {
-		QIXIS_WRITE(cms[0], i);
-		printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
-	}
-}
-
-int board_need_mem_reset(void)
-{
-	return 1;
-}
diff --git a/board/freescale/t1040qds/t1040qds.h b/board/freescale/t1040qds/t1040qds.h
deleted file mode 100644
index 781bcdefc9..0000000000
--- a/board/freescale/t1040qds/t1040qds.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
- */
-
-#ifndef __T1040_QDS_H__
-#define __T1040_QDS_H__
-
-void fdt_fixup_board_enet(void *blob);
-void pci_of_setup(void *blob, bd_t *bd);
-int select_i2c_ch_pca9547(u8 ch, int bus_bum);
-
-#endif
diff --git a/board/freescale/t1040qds/t1040qds_qixis.h b/board/freescale/t1040qds/t1040qds_qixis.h
deleted file mode 100644
index 213d7011db..0000000000
--- a/board/freescale/t1040qds/t1040qds_qixis.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#ifndef __T1040QDS_QIXIS_H__
-#define __T1040QDS_QIXIS_H__
-
-/* Definitions of QIXIS Registers for T1040QDS */
-
-/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
-#define BRDCFG4_EMISEL_MASK		0xE0
-#define BRDCFG4_EMISEL_SHIFT		5
-
-/* BRDCFG5[0:1] controls routing and use of I2C3 & I2C4 ports*/
-#define BRDCFG5_IMX_MASK		0xC0
-#define BRDCFG5_IMX_DIU			0x80
-
-/* BRDCFG9[2] controls EPHY2 Clock */
-#define BRDCFG9_EPHY2_MASK              0x20
-#define BRDCFG9_EPHY2_VAL               0x00
-
-/* BRDCFG15[3] controls LCD Panel Powerdown*/
-#define BRDCFG15_LCDPD_MASK		0x10
-#define BRDCFG15_LCDPD_ENABLED		0x00
-
-/* BRDCFG15[6:7] controls DIU MUX selction*/
-#define BRDCFG15_DIUSEL_MASK		0x03
-#define BRDCFG15_DIUSEL_HDMI		0x00
-
-/* SYSCLK */
-#define QIXIS_SYSCLK_66			0x0
-#define QIXIS_SYSCLK_83			0x1
-#define QIXIS_SYSCLK_100		0x2
-#define QIXIS_SYSCLK_125		0x3
-#define QIXIS_SYSCLK_133		0x4
-#define QIXIS_SYSCLK_150		0x5
-#define QIXIS_SYSCLK_160		0x6
-#define QIXIS_SYSCLK_166		0x7
-#define QIXIS_SYSCLK_64			0x8
-
-/* DDRCLK */
-#define QIXIS_DDRCLK_66			0x0
-#define QIXIS_DDRCLK_100		0x1
-#define QIXIS_DDRCLK_125		0x2
-#define QIXIS_DDRCLK_133		0x3
-
-
-#define QIXIS_SRDS1CLK_122		0x5a
-#define QIXIS_SRDS1CLK_125		0x5e
-#endif
diff --git a/board/freescale/t1040qds/tlb.c b/board/freescale/t1040qds/tlb.c
deleted file mode 100644
index 216b119135..0000000000
--- a/board/freescale/t1040qds/tlb.c
+++ /dev/null
@@ -1,107 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
-	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-
-	/* TLB 1 */
-	/* *I*** - Covers boot page */
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
-	/*
-	 * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the
-	 * SRAM is at 0xfffc0000, it covered the 0xfffff000.
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 0, BOOKE_PAGESZ_256K, 1),
-#else
-	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 0, BOOKE_PAGESZ_4K, 1),
-#endif
-
-	/* *I*G* - CCSRBAR */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 1, BOOKE_PAGESZ_16M, 1),
-
-	/* *I*G* - Flash, localbus */
-	/* This will be changed to *I*G* after relocation to RAM. */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
-		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
-		      0, 2, BOOKE_PAGESZ_256M, 1),
-
-	/* *I*G* - PCI */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 3, BOOKE_PAGESZ_1G, 1),
-
-	/* *I*G* - PCI I/O */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 4, BOOKE_PAGESZ_256K, 1),
-
-	/* Bman/Qman */
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 5, BOOKE_PAGESZ_16M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
-		      CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 6, BOOKE_PAGESZ_16M, 1),
-#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 7, BOOKE_PAGESZ_16M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
-		      CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 8, BOOKE_PAGESZ_16M, 1),
-#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 9, BOOKE_PAGESZ_4M, 1),
-#endif
-#ifdef CONFIG_SYS_NAND_BASE
-	/*
-	 * *I*G - NAND
-	 * entry 14 and 15 has been used hard coded, they will be disabled
-	 * in cpu_init_f, so we use entry 16 for nand.
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 10, BOOKE_PAGESZ_64K, 1),
-#endif
-#ifdef QIXIS_BASE
-	SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 11, BOOKE_PAGESZ_4K, 1),
-#endif
-
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);