diff options
| author | Tom Rini <trini@ti.com> | 2014-12-08 16:35:07 -0500 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2014-12-08 16:35:07 -0500 |
| commit | 272a1acf1ef574356e5da51f7d6b3b07ab4e9b83 (patch) | |
| tree | b65e7b532ac7beb91cfbf3b16f1df76a3a65d59d /board/freescale/t104xrdb | |
| parent | 98d2d5e8c473232dc718763dbec284b7349dcc05 (diff) | |
| parent | af7219de2c66b64ddae0348b3d3fa5072d800dd2 (diff) | |
Merge git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'board/freescale/t104xrdb')
| -rw-r--r-- | board/freescale/t104xrdb/spl.c | 26 |
1 files changed, 16 insertions, 10 deletions
diff --git a/board/freescale/t104xrdb/spl.c b/board/freescale/t104xrdb/spl.c index 3822a37738..e394b121d2 100644 --- a/board/freescale/t104xrdb/spl.c +++ b/board/freescale/t104xrdb/spl.c @@ -34,20 +34,26 @@ unsigned long get_board_ddr_clk(void) void board_init_f(ulong bootflag) { u32 plat_ratio, sys_clk, uart_clk; -#ifdef CONFIG_SPL_NAND_BOOT +#if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND) u32 porsr1, pinctl; + u32 svr = get_svr(); #endif ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; -#ifdef CONFIG_SPL_NAND_BOOT - /* - * There is T1040 SoC issue where NOR, FPGA are inaccessible during - * NAND boot because IFC signals > IFC_AD7 are not enabled. - * This workaround changes RCW source to make all signals enabled. - */ - porsr1 = in_be32(&gur->porsr1); - pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000); - out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl); +#if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND) + if (IS_SVR_REV(svr, 1, 0)) { + /* + * There is T1040 SoC issue where NOR, FPGA are inaccessible + * during NAND boot because IFC signals > IFC_AD7 are not + * enabled. This workaround changes RCW source to make all + * signals enabled. + */ + porsr1 = in_be32(&gur->porsr1); + pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) + | 0x24800000); + out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), + pinctl); + } #endif /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ |