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| author | Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> | 2019-06-13 21:50:28 +0200 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2019-06-14 12:41:26 +0200 |
| commit | d6d383ca27c8121f19cb5fe1b047de330833ce6f (patch) | |
| tree | 66039bbd94086b15c888eb5421c746d13ad7a1de /board/freescale/t208xrdb/t208xrdb.c | |
| parent | b861cfb53c58e06513c3d4518a0d4e5ca57ec2ee (diff) | |
arm: socfpga: provide default SPL_SIZE_LIMIT for gen5
This provides an SPL_SIZE_LIMIT that makes the build check that the SPL
binary loaded from flash fits into the SRAM (64 KiB) and leaves enough
room for global data, heap and stack (512 bytes assumed stack usage).
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Diffstat (limited to 'board/freescale/t208xrdb/t208xrdb.c')
0 files changed, 0 insertions, 0 deletions