diff options
| author | Prabhakar Kushwaha <prabhakar@freescale.com> | 2012-12-18 00:15:45 +0000 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2013-01-30 11:25:09 -0600 |
| commit | ac13eb5de0e465b1bfddab2cdb3a902f583043e8 (patch) | |
| tree | 6e924a651af14ccf472e6c949602c806cfc1ecb9 /board/freescale/t4qds/tlb.c | |
| parent | 2d9f26b69377b3a5953d4422724069d9456c2684 (diff) | |
board/T4240qds:Fix TLB and LAW size of NAND flash
The internal SRAM of Freescale's IFC NAND machine is of 64K and controller's
Address Mask Registers is initialised with the same.
So Update TLB and LAW size of NAND flash accordingly.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'board/freescale/t4qds/tlb.c')
| -rw-r--r-- | board/freescale/t4qds/tlb.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/board/freescale/t4qds/tlb.c b/board/freescale/t4qds/tlb.c index 078a6e415c..80eb511e1d 100644 --- a/board/freescale/t4qds/tlb.c +++ b/board/freescale/t4qds/tlb.c @@ -125,7 +125,7 @@ struct fsl_e_tlb_entry tlb_table[] = { */ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 16, BOOKE_PAGESZ_1M, 1), + 0, 16, BOOKE_PAGESZ_64K, 1), #endif SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |