diff options
| author | Peng Fan <peng.fan@nxp.com> | 2016-12-11 19:24:25 +0800 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2016-12-16 11:38:24 +0100 |
| commit | 0e81982de08fc93118c3dc49cc81def0d3801445 (patch) | |
| tree | b221f86e0280526edfdd51d34d68f7a0b41aa023 /board/freescale | |
| parent | 40913fb595d1f909acbe098b3cbb076c8a635dda (diff) | |
imx: mx6: fix mmdc ch0 clk for 6SL
>From RM, per_periph2_clk_sel option3 is:
"derive clock from 198MHz clock (divided 392MHz PLL2 PFD)."
So fix it.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'board/freescale')
0 files changed, 0 insertions, 0 deletions