diff options
| author | Ingo van Lil <inguin@gmx.de> | 2009-11-24 14:09:21 +0100 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2009-12-05 01:08:53 +0100 |
| commit | 3eb90bad651fab39cffba750ec4421a9c01d60e7 (patch) | |
| tree | 63b21148a041603db252203a422dc465e862e016 /board/freescale | |
| parent | 1c409bc7101a24ecd47a13a4e851845d66dc23ce (diff) | |
Generic udelay() with watchdog support
According to the PPC reference implementation the udelay() function is
responsible for resetting the watchdog timer as frequently as needed.
Most other architectures do not meet that requirement, so long-running
operations might result in a watchdog reset.
This patch adds a generic udelay() function which takes care of
resetting the watchdog before calling an architecture-specific
__udelay().
Signed-off-by: Ingo van Lil <inguin@gmx.de>
Diffstat (limited to 'board/freescale')
| -rw-r--r-- | board/freescale/mpc8313erdb/sdram.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/board/freescale/mpc8313erdb/sdram.c b/board/freescale/mpc8313erdb/sdram.c index cb138296ba..0c4fd6854d 100644 --- a/board/freescale/mpc8313erdb/sdram.c +++ b/board/freescale/mpc8313erdb/sdram.c @@ -72,7 +72,7 @@ static long fixed_sdram(void) * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg], * or the DDR2 controller may fail to initialize correctly. */ - udelay(50000); + __udelay(50000); im->ddr.csbnds[0].csbnds = (msize - 1) >> 24; im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG; |