powerpc/86xx: Rework MPC8641HPCN pci_init_board to use common FSL PCIe code

Remove duplicated code in MPC8641HPCN board and utilize the common
fsl_pcie_init_board().  We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

2 files changed, 2 insertions, 53 deletions

diff --git a/board/freescale/mpc8641hpcn/law.c b/board/freescale/mpc8641hpcn/law.c
index 8c8ce9585a..30a7b706fa 100644
--- a/board/freescale/mpc8641hpcn/law.c
+++ b/board/freescale/mpc8641hpcn/law.c
@@ -53,12 +53,7 @@ struct law_entry law_table[] = {
 #if !defined(CONFIG_SPD_EEPROM)
 	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
 #endif
-#ifdef CONFIG_PCI
-	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
-	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
-	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_1),
-	SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_2),
-#elif defined(CONFIG_RIO)
+#if defined(CONFIG_RIO)
 	SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
 #endif
 	SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
index e95102170d..166ff0c97b 100644
--- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c
+++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
@@ -127,64 +127,18 @@ fixed_sdram(void)
 }
 #endif	/* !defined(CONFIG_SPD_EEPROM) */
 
-
-#if defined(CONFIG_PCI)
-static struct pci_controller pcie1_hose;
-#endif /* CONFIG_PCI */
-
-#ifdef CONFIG_PCIE2
-static struct pci_controller pcie2_hose;
-#endif	/* CONFIG_PCIE2 */
-
-int first_free_busno = 0;
-
 void pci_init_board(void)
 {
-	struct fsl_pci_info pci_info[2];
-	int pcie_ep;
-	int num = 0;
+	fsl_pcie_init_board(0);
 
 #ifdef CONFIG_PCIE1
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
-	volatile ccsr_gur_t *gur = &immap->im_gur;
-	uint devdisr = in_be32(&gur->devdisr);
-	int pcie_configured = is_serdes_configured(PCIE1);
-
-	if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
-		SET_STD_PCIE_INFO(pci_info[num], 1);
-		pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
-		printf("PCIE1: connected to ULI as %s (base addr %lx)\n",
-			pcie_ep ? "Endpoint" : "Root Complex",
-			pci_info[num].regs);
-		first_free_busno = fsl_pci_init_port(&pci_info[num++],
-					&pcie1_hose, first_free_busno);
-
 		/*
 		 * Activate ULI1575 legacy chip by performing a fake
 		 * memory access.  Needed to make ULI RTC work.
 		 */
 		in_be32((unsigned *) ((char *)(CONFIG_SYS_PCIE1_MEM_VIRT
 				       + CONFIG_SYS_PCIE1_MEM_SIZE - 0x1000000)));
-
-	} else {
-		puts("PCIE1: disabled\n");
-	}
-#else
-	puts("PCIE1: disabled\n");
 #endif /* CONFIG_PCIE1 */
-
-#ifdef CONFIG_PCIE2
-	SET_STD_PCIE_INFO(pci_info[num], 2);
-	pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
-	printf("PCIE2: connected as %s (base addr %lx)\n",
-		pcie_ep ? "Endpoint" : "Root Complex",
-		pci_info[num].regs);
-	first_free_busno = fsl_pci_init_port(&pci_info[num++],
-				&pcie2_hose, first_free_busno);
-#else
-	puts("PCIE2: disabled\n");
-#endif /* CONFIG_PCIE2 */
-
 }