summaryrefslogtreecommitdiff
path: root/board/freescale
diff options
context:
space:
mode:
authorShaohui Xie <Shaohui.Xie@nxp.com>2016-04-29 22:07:21 +0800
committerYork Sun <york.sun@nxp.com>2016-05-18 08:51:47 -0700
commit7942550a146f3eaf00add0e13442946365cc9775 (patch)
tree55bd8a4a7199a7cf3401c4a4ef488a722d061c2c /board/freescale
parent76394c9c9139b82e21a6e52da0e7341a3374f4be (diff)
armv8: ls1043ardb: invert irq pin polarity for AQR105 PHY
To use AQR105 PHY's interrupt, we need to invert the IRQ pin polarity by setting relative bit in SCFG_INTPCR register, because AQR105 interrupt is low active but GIC accepts high active. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'board/freescale')
-rw-r--r--board/freescale/ls1043ardb/ls1043ardb.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c
index b1691393e6..14365207da 100644
--- a/board/freescale/ls1043ardb/ls1043ardb.c
+++ b/board/freescale/ls1043ardb/ls1043ardb.c
@@ -82,6 +82,8 @@ int board_early_init_f(void)
int board_init(void)
{
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+
#ifdef CONFIG_FSL_IFC
init_final_memctl_regs();
#endif
@@ -93,6 +95,8 @@ int board_init(void)
#ifdef CONFIG_U_QE
u_qe_init();
#endif
+ /* invert AQR105 IRQ pins polarity */
+ out_be32(&scfg->intpcr, AQR105_IRQ_MASK);
return 0;
}