dm: arm: ls1021a: add i2c DM support

This supports i2c DM and enables CONFIG_DM_I2C
for SoC LS1021A

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>

5 files changed, 264 insertions, 7 deletions

diff --git a/board/freescale/common/dcu_sii9022a.c b/board/freescale/common/dcu_sii9022a.c
index 3bf71abf55..832ae258f1 100644
--- a/board/freescale/common/dcu_sii9022a.c
+++ b/board/freescale/common/dcu_sii9022a.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2019 NXP
  */
 
 #include <asm/io.h>
@@ -63,7 +64,101 @@ int dcu_set_dvi_encoder(struct fb_videomode *videomode)
 	u8 temp;
 	u16 temp1, temp2;
 	u32 temp3;
+#ifdef CONFIG_DM_I2C
+	struct udevice *dev;
+	int ret;
+
+	ret = i2c_get_chip_for_busnum(CONFIG_SYS_I2C_DVI_BUS_NUM,
+				      CONFIG_SYS_I2C_DVI_ADDR,
+				      1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n", __func__,
+		       CONFIG_SYS_I2C_DVI_BUS_NUM);
+		return ret;
+	}
 
+	/* Enable TPI transmitter mode */
+	temp = TPI_TRANS_MODE_ENABLE;
+	dm_i2c_write(dev, TPI_TRANS_MODE_REG, &temp, 1);
+
+	/* Enter into D0 state, full operation */
+	dm_i2c_read(dev, TPI_PWR_STAT_REG, &temp, 1);
+	temp &= ~TPI_PWR_STAT_MASK;
+	temp |= TPI_PWR_STAT_D0;
+	dm_i2c_write(dev, TPI_PWR_STAT_REG, &temp, 1);
+
+	/* Enable source termination */
+	temp = TPI_SET_PAGE_SII9022A;
+	dm_i2c_write(dev, TPI_SET_PAGE_REG, &temp, 1);
+	temp = TPI_SET_OFFSET_SII9022A;
+	dm_i2c_write(dev, TPI_SET_OFFSET_REG, &temp, 1);
+
+	dm_i2c_read(dev, TPI_RW_ACCESS_REG, &temp, 1);
+	temp |= TPI_RW_EN_SRC_TERMIN;
+	dm_i2c_write(dev, TPI_RW_ACCESS_REG, &temp, 1);
+
+	/* Set TPI system control */
+	temp = TPI_SYS_TMDS_OUTPUT | TPI_SYS_AV_NORAML | TPI_SYS_DVI_MODE;
+	dm_i2c_write(dev, TPI_SYS_CTRL_REG, &temp, 1);
+
+	/* Set pixel clock */
+	temp1 = PICOS2KHZ(videomode->pixclock) / 10;
+	temp = (u8)(temp1 & 0xFF);
+	dm_i2c_write(dev, PIXEL_CLK_LSB_REG, &temp, 1);
+	temp = (u8)(temp1 >> 8);
+	dm_i2c_write(dev, PIXEL_CLK_MSB_REG, &temp, 1);
+
+	/* Set total pixels per line */
+	temp1 = videomode->hsync_len + videomode->left_margin +
+		videomode->xres + videomode->right_margin;
+	temp = (u8)(temp1 & 0xFF);
+	dm_i2c_write(dev, TOTAL_PIXELS_LSB_REG, &temp, 1);
+	temp = (u8)(temp1 >> 8);
+	dm_i2c_write(dev, TOTAL_PIXELS_MSB_REG, &temp, 1);
+
+	/* Set total lines */
+	temp2 = videomode->vsync_len + videomode->upper_margin +
+		videomode->yres + videomode->lower_margin;
+	temp = (u8)(temp2 & 0xFF);
+	dm_i2c_write(dev, TOTAL_LINES_LSB_REG, &temp, 1);
+	temp = (u8)(temp2 >> 8);
+	dm_i2c_write(dev, TOTAL_LINES_MSB_REG, &temp, 1);
+
+	/* Set vertical frequency in Hz */
+	temp3 = temp1 * temp2;
+	temp3 = (PICOS2KHZ(videomode->pixclock) * 1000) / temp3;
+	temp1 = (u16)temp3 * 100;
+	temp = (u8)(temp1 & 0xFF);
+	dm_i2c_write(dev, VERT_FREQ_LSB_REG, &temp, 1);
+	temp = (u8)(temp1 >> 8);
+	dm_i2c_write(dev, VERT_FREQ_MSB_REG, &temp, 1);
+
+	/* Set TPI input bus and pixel repetition data */
+	temp = TPI_INBUS_CLOCK_RATIO_1 | TPI_INBUS_FULL_PIXEL_WIDE |
+		TPI_INBUS_RISING_EDGE;
+	dm_i2c_write(dev, TPI_INBUS_FMT_REG, &temp, 1);
+
+	/* Set TPI AVI Input format data */
+	temp = TPI_INPUT_CLR_DEPTH_8BIT | TPI_INPUT_VRANGE_EXPAN_AUTO |
+		TPI_INPUT_CLR_RGB;
+	dm_i2c_write(dev, TPI_INPUT_FMT_REG, &temp, 1);
+
+	/* Set TPI AVI Output format data */
+	temp = TPI_OUTPUT_CLR_DEPTH_8BIT | TPI_OUTPUT_VRANGE_COMPRE_AUTO |
+		TPI_OUTPUT_CLR_HDMI_RGB;
+	dm_i2c_write(dev, TPI_OUTPUT_FMT_REG, &temp, 1);
+
+	/* Set TPI audio configuration write data */
+	temp = TPI_AUDIO_PASS_BASIC;
+	dm_i2c_write(dev, TPI_AUDIO_HANDING_REG, &temp, 1);
+
+	temp = TPI_AUDIO_INTF_I2S | TPI_AUDIO_INTF_NORMAL |
+		TPI_AUDIO_TYPE_PCM;
+	dm_i2c_write(dev, TPI_AUDIO_INTF_REG, &temp, 1);
+
+	temp = TPI_AUDIO_SAMP_SIZE_16BIT | TPI_AUDIO_SAMP_FREQ_44K;
+	dm_i2c_write(dev, TPI_AUDIO_FREQ_REG, &temp, 1);
+#else
 	i2c_set_bus_num(CONFIG_SYS_I2C_DVI_BUS_NUM);
 
 	/* Enable TPI transmitter mode */
@@ -147,6 +242,7 @@ int dcu_set_dvi_encoder(struct fb_videomode *videomode)
 
 	temp = TPI_AUDIO_SAMP_SIZE_16BIT | TPI_AUDIO_SAMP_FREQ_44K;
 	i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_AUDIO_FREQ_REG, 1, &temp, 1);
+#endif
 
 	return 0;
 }
diff --git a/board/freescale/common/diu_ch7301.c b/board/freescale/common/diu_ch7301.c
index 435b4a3f1a..7f11123e6f 100644
--- a/board/freescale/common/diu_ch7301.c
+++ b/board/freescale/common/diu_ch7301.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2019 NXP
  * Authors: Priyanka Jain <Priyanka.Jain@freescale.com>
  *	    Wang Dongsheng <dongsheng.wang@freescale.com>
  *
@@ -51,6 +52,85 @@ int diu_set_dvi_encoder(unsigned int pixclock)
 	u8 temp;
 
 	temp = I2C_DVI_TEST_PATTERN_VAL;
+#ifdef CONFIG_DM_I2C
+	struct udevice *dev;
+
+	ret = i2c_get_chip_for_busnum(CONFIG_SYS_I2C_DVI_BUS_NUM,
+				      CONFIG_SYS_I2C_DVI_ADDR,
+				      1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n", __func__,
+		       CONFIG_SYS_I2C_DVI_BUS_NUM);
+		return ret;
+	}
+	ret = dm_i2c_write(dev, I2C_DVI_TEST_PATTERN_REG, &temp, 1);
+	if (ret) {
+		puts("I2C: failed to select proper dvi test pattern\n");
+		return ret;
+	}
+	temp = I2C_DVI_INPUT_DATA_FORMAT_VAL;
+	ret = dm_i2c_write(dev, I2C_DVI_INPUT_DATA_FORMAT_REG, &temp, 1);
+	if (ret) {
+		puts("I2C: failed to select dvi input data format\n");
+		return ret;
+	}
+
+	/* Set Sync polarity register */
+	temp = I2C_DVI_SYNC_POLARITY_VAL;
+	ret = dm_i2c_write(dev, I2C_DVI_SYNC_POLARITY_REG, &temp, 1);
+	if (ret) {
+		puts("I2C: failed to select dvi syc polarity\n");
+		return ret;
+	}
+
+	/* Set PLL registers based on pixel clock rate*/
+	if (pixclock > 65000000) {
+		temp = I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL;
+		ret = dm_i2c_write(dev, I2C_DVI_PLL_CHARGE_CNTL_REG, &temp, 1);
+		if (ret) {
+			puts("I2C: failed to select dvi pll charge_cntl\n");
+			return ret;
+		}
+		temp = I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL;
+		ret = dm_i2c_write(dev, I2C_DVI_PLL_DIVIDER_REG, &temp, 1);
+		if (ret) {
+			puts("I2C: failed to select dvi pll divider\n");
+			return ret;
+		}
+		temp = I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL;
+		ret = dm_i2c_write(dev, I2C_DVI_PLL_FILTER_REG, &temp, 1);
+		if (ret) {
+			puts("I2C: failed to select dvi pll filter\n");
+			return ret;
+		}
+	} else {
+		temp = I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL;
+		ret = dm_i2c_write(dev, I2C_DVI_PLL_CHARGE_CNTL_REG, &temp, 1);
+		if (ret) {
+			puts("I2C: failed to select dvi pll charge_cntl\n");
+			return ret;
+		}
+		temp = I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL;
+		ret = dm_i2c_write(dev, I2C_DVI_PLL_DIVIDER_REG, &temp, 1);
+		if (ret) {
+			puts("I2C: failed to select dvi pll divider\n");
+			return ret;
+		}
+		temp = I2C_DVI_PLL_FILTER_LOW_SPEED_VAL;
+		ret = dm_i2c_write(dev, I2C_DVI_PLL_FILTER_REG, &temp, 1);
+		if (ret) {
+			puts("I2C: failed to select dvi pll filter\n");
+			return ret;
+		}
+	}
+
+	temp = I2C_DVI_POWER_MGMT_VAL;
+	ret = dm_i2c_write(dev, I2C_DVI_POWER_MGMT_REG, &temp, 1);
+	if (ret) {
+		puts("I2C: failed to select dvi power mgmt\n");
+		return ret;
+	}
+#else
 	ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_TEST_PATTERN_REG, 1,
 			&temp, 1);
 	if (ret) {
@@ -128,6 +208,7 @@ int diu_set_dvi_encoder(unsigned int pixclock)
 		puts("I2C: failed to select dvi power mgmt\n");
 		return ret;
 	}
+#endif
 
 	udelay(500);
 
diff --git a/board/freescale/ls1021aqds/dcu.c b/board/freescale/ls1021aqds/dcu.c
index c4eac5e302..b648a7872b 100644
--- a/board/freescale/ls1021aqds/dcu.c
+++ b/board/freescale/ls1021aqds/dcu.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2019 NXP
  *
  * FSL DCU Framebuffer driver
  */
@@ -15,11 +16,23 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static int select_i2c_ch_pca9547(u8 ch)
+static int select_i2c_ch_pca9547(u8 ch, int bus_num)
 {
 	int ret;
+#ifdef CONFIG_DM_I2C
+	struct udevice *dev;
 
+	ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
+				      1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n", __func__,
+		       bus_num);
+		return ret;
+	}
+	ret = dm_i2c_write(dev, 0, &ch, 1);
+#else
 	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+#endif
 	if (ret) {
 		puts("PCA: failed to select proper channel\n");
 		return ret;
@@ -51,6 +64,28 @@ int platform_dcu_init(struct fb_info *fbinfo,
 	u8 ch;
 
 	/* Mux I2C3+I2C4 as HSYNC+VSYNC */
+#ifdef CONFIG_DM_I2C
+	struct udevice *dev;
+
+	/* QIXIS device mount on I2C1 bus*/
+	ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_QIXIS_ADDR,
+				      1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n", __func__,
+		       0);
+		return ret;
+	}
+	ret = dm_i2c_read(dev, QIXIS_DCU_BRDCFG5, &ch, 1);
+	if (ret) {
+		printf("Error: failed to read I2C @%02x\n",
+		       CONFIG_SYS_I2C_QIXIS_ADDR);
+		return ret;
+	}
+	ch &= 0x1F;
+	ch |= 0xA0;
+	ret = dm_i2c_write(dev, QIXIS_DCU_BRDCFG5, &ch, 1);
+
+#else
 	ret = i2c_read(CONFIG_SYS_I2C_QIXIS_ADDR, QIXIS_DCU_BRDCFG5,
 		       1, &ch, 1);
 	if (ret) {
@@ -62,6 +97,7 @@ int platform_dcu_init(struct fb_info *fbinfo,
 	ch |= 0xA0;
 	ret = i2c_write(CONFIG_SYS_I2C_QIXIS_ADDR, QIXIS_DCU_BRDCFG5,
 			1, &ch, 1);
+#endif
 	if (ret) {
 		printf("Error: failed to write I2C @%02x\n",
 		       CONFIG_SYS_I2C_QIXIS_ADDR);
@@ -76,10 +112,14 @@ int platform_dcu_init(struct fb_info *fbinfo,
 		pixval = 1000000000 / dcu_fb_videomode->pixclock;
 		pixval *= 1000;
 
+#ifndef CONFIG_DM_I2C
 		i2c_set_bus_num(CONFIG_SYS_I2C_DVI_BUS_NUM);
-		select_i2c_ch_pca9547(I2C_MUX_CH_CH7301);
+#endif
+		select_i2c_ch_pca9547(I2C_MUX_CH_CH7301,
+				      CONFIG_SYS_I2C_DVI_BUS_NUM);
 		diu_set_dvi_encoder(pixval);
-		select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+		select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT,
+				      CONFIG_SYS_I2C_DVI_BUS_NUM);
 	} else {
 		return 0;
 	}
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c
index b7f8f1d578..1ae822e510 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2019 NXP
  */
 
 #include <common.h>
@@ -139,11 +140,23 @@ unsigned long get_board_ddr_clk(void)
 	return 66666666;
 }
 
-int select_i2c_ch_pca9547(u8 ch)
+int select_i2c_ch_pca9547(u8 ch, int bus_num)
 {
 	int ret;
+#ifdef CONFIG_DM_I2C
+	struct udevice *dev;
 
+	ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
+				      1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n", __func__,
+		       bus_num);
+		return ret;
+	}
+	ret = dm_i2c_write(dev, 0, &ch, 1);
+#else
 	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+#endif
 	if (ret) {
 		puts("PCA: failed to select proper channel\n");
 		return ret;
@@ -158,8 +171,10 @@ int dram_init(void)
 	 * When resuming from deep sleep, the I2C channel may not be
 	 * in the default channel. So, switch to the default channel
 	 * before accessing DDR SPD.
+	 *
+	 * PCA9547(0x77) mount on I2C1 bus
 	 */
-	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
 	return fsl_initdram();
 }
 
@@ -408,7 +423,7 @@ int board_init(void)
 	erratum_a009942_check_cpo();
 #endif
 
-	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
 
 #ifndef CONFIG_SYS_FSL_NO_SERDES
 	fsl_serdes_init();
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c
index 497dce5f0f..d1ff7b8ba6 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2019 NXP
  */
 
 #include <common.h>
@@ -447,14 +448,37 @@ void board_init_f(ulong dummy)
 /* program the regulator (MC34VR500) to support deep sleep */
 void ls1twr_program_regulator(void)
 {
-	unsigned int i2c_bus;
 	u8 i2c_device_id;
 
 #define LS1TWR_I2C_BUS_MC34VR500	1
 #define MC34VR500_ADDR			0x8
 #define MC34VR500_DEVICEID		0x4
 #define MC34VR500_DEVICEID_MASK		0x0f
+#ifdef CONFIG_DM_I2C
+	struct udevice *dev;
+	int ret;
+
+	ret = i2c_get_chip_for_busnum(LS1TWR_I2C_BUS_MC34VR500, MC34VR500_ADDR,
+				      1, &dev);
+	if (ret) {
+		printf("%s: Cannot find udev for a bus %d\n", __func__,
+		       LS1TWR_I2C_BUS_MC34VR500);
+		return;
+	}
+	i2c_device_id = dm_i2c_reg_read(dev, 0x0) &
+					MC34VR500_DEVICEID_MASK;
+	if (i2c_device_id != MC34VR500_DEVICEID) {
+		printf("The regulator (MC34VR500) does not exist. The device does not support deep sleep.\n");
+		return;
+	}
 
+	dm_i2c_reg_write(dev, 0x31, 0x4);
+	dm_i2c_reg_write(dev, 0x4d, 0x4);
+	dm_i2c_reg_write(dev, 0x6d, 0x38);
+	dm_i2c_reg_write(dev, 0x6f, 0x37);
+	dm_i2c_reg_write(dev, 0x71, 0x30);
+#else
+	unsigned int i2c_bus;
 	i2c_bus = i2c_get_bus_num();
 	i2c_set_bus_num(LS1TWR_I2C_BUS_MC34VR500);
 	i2c_device_id = i2c_reg_read(MC34VR500_ADDR, 0x0) &
@@ -471,6 +495,7 @@ void ls1twr_program_regulator(void)
 	i2c_reg_write(MC34VR500_ADDR, 0x71, 0x30);
 
 	i2c_set_bus_num(i2c_bus);
+#endif
 }
 #endif