m68k: mcf5445x: move early ddr init as board-specific

For certain boot types and sbf, for V4 cpu's, an early ddr/sdram init
is required. This patch moves this ddr/sdram early initalization
away from start.S (to be board related).

Signed-off-by: Angelo Dureghello <angelo@sysam.it>

6 files changed, 288 insertions, 0 deletions

diff --git a/board/freescale/m54418twr/Makefile b/board/freescale/m54418twr/Makefile
index 371c04abe8..4ef1e5aee9 100644
--- a/board/freescale/m54418twr/Makefile
+++ b/board/freescale/m54418twr/Makefile
@@ -5,3 +5,5 @@
 #
 
 obj-y	= m54418twr.o
+extra-y	+= sbf_dram_init.o
+
diff --git a/board/freescale/m54418twr/sbf_dram_init.S b/board/freescale/m54418twr/sbf_dram_init.S
new file mode 100644
index 0000000000..7f25793fe3
--- /dev/null
+++ b/board/freescale/m54418twr/sbf_dram_init.S
@@ -0,0 +1,86 @@
+/*
+ * Board-specific sbf ddr/sdram init.
+ *
+ * (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+.global sbf_dram_init
+.text
+
+sbf_dram_init:
+	move.l	#0xFC04002D, %a1
+	move.b	#46, (%a1)		/* DDR */
+
+	/* slew settings */
+	move.l	#0xEC094060, %a1
+	move.b	#0, (%a1)
+
+	/* use vco instead of cpu*2 clock for ddr clock */
+	move.l	#0xEC09001A, %a1
+	move.w	#0xE01D, (%a1)
+
+	/* DDR settings */
+	move.l	#0xFC0B8180, %a1
+	move.l	#0x00000000, (%a1)
+	move.l	#0x40000000, (%a1)
+
+	move.l	#0xFC0B81AC, %a1
+	move.l	#0x01030203, (%a1)
+
+	move.l	#0xFC0B8000, %a1
+	move.l	#0x01010101, (%a1)+	/* 0x00 */
+	move.l	#0x00000101, (%a1)+	/* 0x04 */
+	move.l	#0x01010100, (%a1)+	/* 0x08 */
+	move.l	#0x01010000, (%a1)+	/* 0x0C */
+	move.l	#0x00010101, (%a1)+	/* 0x10 */
+	move.l	#0xFC0B8018, %a1
+	move.l	#0x00010100, (%a1)+	/* 0x18 */
+	move.l	#0x00000001, (%a1)+	/* 0x1C */
+	move.l	#0x01000001, (%a1)+	/* 0x20 */
+	move.l	#0x00000100, (%a1)+	/* 0x24 */
+	move.l	#0x00010001, (%a1)+	/* 0x28 */
+	move.l	#0x00000200, (%a1)+	/* 0x2C */
+	move.l	#0x01000002, (%a1)+	/* 0x30 */
+	move.l	#0x00000000, (%a1)+	/* 0x34 */
+	move.l	#0x00000100, (%a1)+	/* 0x38 */
+	move.l	#0x02000100, (%a1)+	/* 0x3C */
+	move.l	#0x02000407, (%a1)+	/* 0x40 */
+	move.l	#0x02030007, (%a1)+	/* 0x44 */
+	move.l	#0x02000100, (%a1)+	/* 0x48 */
+	move.l	#0x0A030203, (%a1)+	/* 0x4C */
+	move.l	#0x00020708, (%a1)+	/* 0x50 */
+	move.l	#0x00050008, (%a1)+	/* 0x54 */
+	move.l	#0x04030002, (%a1)+	/* 0x58 */
+	move.l	#0x00000004, (%a1)+	/* 0x5C */
+	move.l	#0x020A0000, (%a1)+	/* 0x60 */
+	move.l	#0x0C00000E, (%a1)+	/* 0x64 */
+	move.l	#0x00002004, (%a1)+	/* 0x68 */
+	move.l	#0x00000000, (%a1)+	/* 0x6C */
+	move.l	#0x00100010, (%a1)+	/* 0x70 */
+	move.l	#0x00100010, (%a1)+	/* 0x74 */
+	move.l	#0x00000000, (%a1)+	/* 0x78 */
+	move.l	#0x07990000, (%a1)+	/* 0x7C */
+	move.l	#0xFC0B80A0, %a1
+	move.l	#0x00000000, (%a1)+	/* 0xA0 */
+	move.l	#0x00C80064, (%a1)+	/* 0xA4 */
+	move.l	#0x44520002, (%a1)+	/* 0xA8 */
+	move.l	#0x00C80023, (%a1)+	/* 0xAC */
+	move.l	#0xFC0B80B4, %a1
+	move.l	#0x0000C350, (%a1)	/* 0xB4 */
+	move.l	#0xFC0B80E0, %a1
+	move.l	#0x04000000, (%a1)+	/* 0xE0 */
+	move.l	#0x03000304, (%a1)+	/* 0xE4 */
+	move.l	#0x40040000, (%a1)+	/* 0xE8 */
+	move.l	#0xC0004004, (%a1)+	/* 0xEC */
+	move.l	#0x0642C000, (%a1)+	/* 0xF0 */
+	move.l	#0x00000642, (%a1)+	/* 0xF4 */
+	move.l	#0xFC0B8024, %a1
+	tpf
+	move.l	#0x01000100, (%a1)	/* 0x24 */
+
+	move.l	#0x2000, %d1
+	bsr	asm_delay
+
+	rts
diff --git a/board/freescale/m54451evb/Makefile b/board/freescale/m54451evb/Makefile
index 700ea2a74c..ec4956b8d6 100644
--- a/board/freescale/m54451evb/Makefile
+++ b/board/freescale/m54451evb/Makefile
@@ -6,3 +6,4 @@
 #
 
 obj-y	= m54451evb.o
+extra-y	+= sbf_dram_init.o
diff --git a/board/freescale/m54451evb/sbf_dram_init.S b/board/freescale/m54451evb/sbf_dram_init.S
new file mode 100644
index 0000000000..f8da3584fe
--- /dev/null
+++ b/board/freescale/m54451evb/sbf_dram_init.S
@@ -0,0 +1,97 @@
+/*
+ * Board-specific sbf ddr/sdram init.
+ *
+ * (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+ #include <config.h>
+
+.global sbf_dram_init
+.text
+
+sbf_dram_init:
+	/* Dram Initialization a1, a2, and d0 */
+	/* mscr sdram */
+	move.l	#0xFC0A4074, %a1
+	move.b	#(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1)
+	nop
+
+	/* SDRAM Chip 0 and 1 */
+	move.l	#0xFC0B8110, %a1
+	move.l	#0xFC0B8114, %a2
+
+	/* calculate the size */
+	move.l	#0x13, %d1
+	move.l	#(CONFIG_SYS_SDRAM_SIZE), %d2
+#ifdef CONFIG_SYS_SDRAM_BASE1
+	lsr.l	#1, %d2
+#endif
+
+dramsz_loop:
+	lsr.l	#1, %d2
+	add.l	#1, %d1
+	cmp.l	#1, %d2
+	bne	dramsz_loop
+#ifdef CONFIG_SYS_NAND_BOOT
+	beq	asm_nand_chk_status
+#endif
+	/* SDRAM Chip 0 and 1 */
+	move.l	#(CONFIG_SYS_SDRAM_BASE), (%a1)
+	or.l	%d1, (%a1)
+#ifdef CONFIG_SYS_SDRAM_BASE1
+	move.l	#(CONFIG_SYS_SDRAM_BASE1), (%a2)
+	or.l	%d1, (%a2)
+#endif
+	nop
+
+	/* dram cfg1 and cfg2 */
+	move.l	#0xFC0B8008, %a1
+	move.l	#(CONFIG_SYS_SDRAM_CFG1), (%a1)
+	nop
+	move.l	#0xFC0B800C, %a2
+	move.l	#(CONFIG_SYS_SDRAM_CFG2), (%a2)
+	nop
+
+	move.l	#0xFC0B8000, %a1	/* Mode */
+	move.l	#0xFC0B8004, %a2	/* Ctrl */
+
+	/* Issue PALL */
+	move.l	#(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
+	nop
+
+	move.l	#1000, %d1
+	bsr	asm_delay
+
+	/* Issue PALL */
+	move.l	#(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
+	nop
+
+	/* Perform two refresh cycles */
+	move.l	#(CONFIG_SYS_SDRAM_CTRL + 4), %d0
+	nop
+	move.l	%d0, (%a2)
+	move.l	%d0, (%a2)
+	nop
+
+	/* Issue LEMR */
+	move.l	#(CONFIG_SYS_SDRAM_MODE), (%a1)
+	nop
+	move.l	#(CONFIG_SYS_SDRAM_EMOD), (%a1)
+
+	move.l	#500, %d1
+	bsr	asm_delay
+
+	move.l	#(CONFIG_SYS_SDRAM_CTRL), %d1
+	and.l	#0x7FFFFFFF, %d1
+
+	or.l	#0x10000C00, %d1
+
+	move.l	%d1, (%a2)
+	nop
+
+	move.l	#2000, %d1
+	bsr	asm_delay
+
+	rts
diff --git a/board/freescale/m54455evb/Makefile b/board/freescale/m54455evb/Makefile
index 1c775fadb8..ecbc3ca044 100644
--- a/board/freescale/m54455evb/Makefile
+++ b/board/freescale/m54455evb/Makefile
@@ -6,3 +6,4 @@
 #
 
 obj-y	= m54455evb.o
+extra-y	+= sbf_dram_init.o
diff --git a/board/freescale/m54455evb/sbf_dram_init.S b/board/freescale/m54455evb/sbf_dram_init.S
new file mode 100644
index 0000000000..2bf95a93a7
--- /dev/null
+++ b/board/freescale/m54455evb/sbf_dram_init.S
@@ -0,0 +1,101 @@
+/*
+ * Board-specific sbf ddr/sdram init.
+ *
+ * (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+ #include <config.h>
+
+.global sbf_dram_init
+.text
+
+sbf_dram_init:
+	/* Dram Initialization a1, a2, and d0 */
+	/* mscr sdram */
+	move.l	#0xFC0A4074, %a1
+	move.b	#(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1)
+	nop
+
+	/* SDRAM Chip 0 and 1 */
+	move.l	#0xFC0B8110, %a1
+	move.l	#0xFC0B8114, %a2
+
+	/* calculate the size */
+	move.l	#0x13, %d1
+	move.l	#(CONFIG_SYS_SDRAM_SIZE), %d2
+#ifdef CONFIG_SYS_SDRAM_BASE1
+	lsr.l	#1, %d2
+#endif
+
+dramsz_loop:
+	lsr.l	#1, %d2
+	add.l	#1, %d1
+	cmp.l	#1, %d2
+	bne	dramsz_loop
+#ifdef CONFIG_SYS_NAND_BOOT
+	beq	asm_nand_chk_status
+#endif
+	/* SDRAM Chip 0 and 1 */
+	move.l	#(CONFIG_SYS_SDRAM_BASE), (%a1)
+	or.l	%d1, (%a1)
+#ifdef CONFIG_SYS_SDRAM_BASE1
+	move.l	#(CONFIG_SYS_SDRAM_BASE1), (%a2)
+	or.l	%d1, (%a2)
+#endif
+	nop
+
+	/* dram cfg1 and cfg2 */
+	move.l	#0xFC0B8008, %a1
+	move.l	#(CONFIG_SYS_SDRAM_CFG1), (%a1)
+	nop
+	move.l	#0xFC0B800C, %a2
+	move.l	#(CONFIG_SYS_SDRAM_CFG2), (%a2)
+	nop
+
+	move.l	#0xFC0B8000, %a1	/* Mode */
+	move.l	#0xFC0B8004, %a2	/* Ctrl */
+
+	/* Issue PALL */
+	move.l	#(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
+	nop
+
+	/* Issue LEMR */
+	move.l	#(CONFIG_SYS_SDRAM_EMOD + 0x408), (%a1)
+	nop
+	move.l	#(CONFIG_SYS_SDRAM_MODE + 0x300), (%a1)
+	nop
+
+	move.l	#1000, %d1
+	bsr	asm_delay
+
+	/* Issue PALL */
+	move.l	#(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
+	nop
+
+	/* Perform two refresh cycles */
+	move.l	#(CONFIG_SYS_SDRAM_CTRL + 4), %d0
+	nop
+	move.l	%d0, (%a2)
+	move.l	%d0, (%a2)
+	nop
+
+	move.l	#(CONFIG_SYS_SDRAM_MODE + 0x200), (%a1)
+	nop
+
+	move.l	#500, %d1
+	bsr	asm_delay
+
+	move.l	#(CONFIG_SYS_SDRAM_CTRL), %d1
+	and.l	#0x7FFFFFFF, %d1
+
+	or.l	#0x10000C00, %d1
+
+	move.l	%d1, (%a2)
+	nop
+
+	move.l	#2000, %d1
+	bsr	asm_delay
+
+	rts