Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

16 files changed, 315 insertions, 45 deletions

diff --git a/board/freescale/c29xpcie/MAINTAINERS b/board/freescale/c29xpcie/MAINTAINERS
index db2e5e3bd3..33088396f5 100644
--- a/board/freescale/c29xpcie/MAINTAINERS
+++ b/board/freescale/c29xpcie/MAINTAINERS
@@ -6,3 +6,5 @@ F:	include/configs/C29XPCIE.h
 F:	configs/C29XPCIE_defconfig
 F:	configs/C29XPCIE_NAND_defconfig
 F:	configs/C29XPCIE_SPIFLASH_defconfig
+F:	configs/C29XPCIE_NOR_SECBOOT_defconfig
+F:	configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig
diff --git a/board/freescale/corenet_ds/MAINTAINERS b/board/freescale/corenet_ds/MAINTAINERS
index c8ca6746f1..745847cdba 100644
--- a/board/freescale/corenet_ds/MAINTAINERS
+++ b/board/freescale/corenet_ds/MAINTAINERS
@@ -27,3 +27,4 @@ F:	configs/P5040DS_defconfig
 F:	configs/P5040DS_NAND_defconfig
 F:	configs/P5040DS_SDCARD_defconfig
 F:	configs/P5040DS_SPIFLASH_defconfig
+F:	configs/P5040DS_SECURE_BOOT_defconfig
diff --git a/board/freescale/t102xqds/ddr.c b/board/freescale/t102xqds/ddr.c
index 46fc64e528..2d4d10f351 100644
--- a/board/freescale/t102xqds/ddr.c
+++ b/board/freescale/t102xqds/ddr.c
@@ -11,6 +11,7 @@
 #include <fsl_ddr_sdram.h>
 #include <fsl_ddr_dimm_params.h>
 #include <asm/fsl_law.h>
+#include <asm/mpc85xx_gpio.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -152,6 +153,19 @@ found:
 #endif
 }
 
+#if defined(CONFIG_DEEP_SLEEP)
+void board_mem_sleep_setup(void)
+{
+	void __iomem *qixis_base = (void *)QIXIS_BASE;
+
+	/* does not provide HW signals for power management */
+	clrbits_8(qixis_base + 0x21, 0x2);
+	/* Disable MCKE isolation */
+	gpio_set_value(2, 0);
+	udelay(1);
+}
+#endif
+
 phys_size_t initdram(int board_type)
 {
 	phys_size_t dram_size;
@@ -166,5 +180,10 @@ phys_size_t initdram(int board_type)
 	/* DDR has been initialised by first stage boot loader */
 	dram_size =  fsl_ddr_sdram_size();
 #endif
+
+#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
+	fsl_dp_resume();
+#endif
+
 	return dram_size;
 }
diff --git a/board/freescale/t102xqds/t102xqds.c b/board/freescale/t102xqds/t102xqds.c
index f3141b58e8..708afcaebf 100644
--- a/board/freescale/t102xqds/t102xqds.c
+++ b/board/freescale/t102xqds/t102xqds.c
@@ -19,10 +19,10 @@
 #include <asm/fsl_liodn.h>
 #include <fm_eth.h>
 #include <hwconfig.h>
-#include <asm/mpc85xx_gpio.h>
 #include "../common/qixis.h"
 #include "t102xqds.h"
 #include "t102xqds_qixis.h"
+#include "../common/sleep.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -242,6 +242,16 @@ void board_retimer_ds125df111_init(void)
 	i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
 }
 
+int board_early_init_f(void)
+{
+#if defined(CONFIG_DEEP_SLEEP)
+	if (is_warm_boot())
+		fsl_dp_disable_console();
+#endif
+
+	return 0;
+}
+
 int board_early_init_r(void)
 {
 #ifdef CONFIG_SYS_FLASH_BASE
@@ -395,14 +405,3 @@ void qixis_dump_switch(void)
 		printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
 	}
 }
-
-#ifdef CONFIG_DEEP_SLEEP
-void board_mem_sleep_setup(void)
-{
-	/* does not provide HW signals for power management */
-	QIXIS_WRITE(pwr_ctl[1], (QIXIS_READ(pwr_ctl[1]) & ~0x2));
-	/* Disable MCKE isolation */
-	gpio_set_value(2, 0);
-	udelay(1);
-}
-#endif
diff --git a/board/freescale/t102xrdb/cpld.h b/board/freescale/t102xrdb/cpld.h
index 5a3100f607..db50f818fb 100644
--- a/board/freescale/t102xrdb/cpld.h
+++ b/board/freescale/t102xrdb/cpld.h
@@ -43,3 +43,7 @@ void cpld_write(unsigned int reg, u8 value);
 #define CPLD_LBMAP_RESET	0xFF
 #define CPLD_LBMAP_SHIFT	0x03
 #define CPLD_BOOT_SEL	   0x80
+
+#define CPLD_PCIE_SGMII_MUX	0x80
+#define CPLD_OVERRIDE_BOOT_EN	0x01
+#define CPLD_OVERRIDE_MUX_EN	0x02 /* PCIE/2.5G-SGMII mux override enable */
diff --git a/board/freescale/t102xrdb/ddr.c b/board/freescale/t102xrdb/ddr.c
index a20330b1d0..a2a8f4ccf0 100644
--- a/board/freescale/t102xrdb/ddr.c
+++ b/board/freescale/t102xrdb/ddr.c
@@ -11,6 +11,7 @@
 #include <fsl_ddr_sdram.h>
 #include <fsl_ddr_dimm_params.h>
 #include <asm/fsl_law.h>
+#include <asm/mpc85xx_gpio.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -136,6 +137,19 @@ found:
 #endif
 }
 
+#if defined(CONFIG_DEEP_SLEEP)
+void board_mem_sleep_setup(void)
+{
+	void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE;
+
+	/* does not provide HW signals for power management */
+	clrbits_8(cpld_base + 0x17, 0x40);
+	/* Disable MCKE isolation */
+	gpio_set_value(2, 0);
+	udelay(1);
+}
+#endif
+
 phys_size_t initdram(int board_type)
 {
 	phys_size_t dram_size;
@@ -150,5 +164,10 @@ phys_size_t initdram(int board_type)
 	/* DDR has been initialised by first stage boot loader */
 	dram_size =  fsl_ddr_sdram_size();
 #endif
+
+#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
+	fsl_dp_resume();
+#endif
+
 	return dram_size;
 }
diff --git a/board/freescale/t102xrdb/eth_t102xrdb.c b/board/freescale/t102xrdb/eth_t102xrdb.c
index 2e400c4ebf..f611ff07e9 100644
--- a/board/freescale/t102xrdb/eth_t102xrdb.c
+++ b/board/freescale/t102xrdb/eth_t102xrdb.c
@@ -21,6 +21,7 @@
 #include <phy.h>
 #include <asm/fsl_dtsec.h>
 #include <asm/fsl_serdes.h>
+#include "../common/fman.h"
 
 int board_eth_init(bd_t *bis)
 {
@@ -51,15 +52,22 @@ int board_eth_init(bd_t *bis)
 	/* Register the 10G MDIO bus */
 	fm_memac_mdio_init(bis, &tgec_mdio_info);
 
-	/* Set the two on-board RGMII PHY address */
-	fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
+	/* Set the on-board RGMII PHY address */
 	fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR);
 
 	switch (srds_s1) {
 	case 0x95:
-		/* 10G XFI with Aquantia PHY */
+		/* set the on-board RGMII2  PHY */
+		fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
+
+		/* set 10G XFI with Aquantia AQR105 PHY */
 		fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
 		break;
+	case 0x77:
+	case 0x135:
+		/* set the on-board 2.5G SGMII AQR105 PHY */
+		fm_info_set_phy_address(FM1_DTSEC3, SGMII_PHY1_ADDR);
+		break;
 	default:
 		printf("SerDes protocol 0x%x is not supported on T102xRDB\n",
 		       srds_s1);
@@ -73,6 +81,10 @@ int board_eth_init(bd_t *bis)
 			dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
 			fm_info_set_mdio(i, dev);
 			break;
+		case PHY_INTERFACE_MODE_SGMII_2500:
+			dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
+			fm_info_set_mdio(i, dev);
+			break;
 		default:
 			break;
 		}
@@ -95,6 +107,18 @@ int board_eth_init(bd_t *bis)
 	return pci_eth_init(bis);
 }
 
+void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
+			      enum fm_port port, int offset)
+{
+	if ((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) &&
+	    (port == FM1_DTSEC3)) {
+		fdt_set_phy_handle(fdt, compat, addr, "sg_2500_aqr105_phy4");
+		fdt_setprop(fdt, offset, "phy-connection-type",
+			    "sgmii-2500", 10);
+		fdt_status_disabled_by_alias(fdt, "xg_aqr105_phy3");
+	}
+}
+
 void fdt_fixup_board_enet(void *fdt)
 {
 }
diff --git a/board/freescale/t102xrdb/spl.c b/board/freescale/t102xrdb/spl.c
index dd2dec4412..1a3a996439 100644
--- a/board/freescale/t102xrdb/spl.c
+++ b/board/freescale/t102xrdb/spl.c
@@ -11,6 +11,7 @@
 #include <mmc.h>
 #include <fsl_esdhc.h>
 #include <spi_flash.h>
+#include "../common/sleep.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -42,6 +43,12 @@ void board_init_f(ulong bootflag)
 
 	console_init_f();
 
+#ifdef CONFIG_DEEP_SLEEP
+	/* disable the console if boot from deep sleep */
+	if (is_warm_boot())
+		fsl_dp_disable_console();
+#endif
+
 	/* initialize selected port with appropriate baud rate */
 	sys_clk = get_board_sys_clk();
 	plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
diff --git a/board/freescale/t102xrdb/t102xrdb.c b/board/freescale/t102xrdb/t102xrdb.c
index f5c438ded3..e196f12ac7 100644
--- a/board/freescale/t102xrdb/t102xrdb.c
+++ b/board/freescale/t102xrdb/t102xrdb.c
@@ -16,10 +16,10 @@
 #include <asm/fsl_serdes.h>
 #include <asm/fsl_portals.h>
 #include <asm/fsl_liodn.h>
-#include <asm/mpc85xx_gpio.h>
 #include <fm_eth.h>
 #include "t102xrdb.h"
 #include "cpld.h"
+#include "../common/sleep.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -27,6 +27,11 @@ int checkboard(void)
 {
 	struct cpu_type *cpu = gd->arch.cpu;
 	static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
+	ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 srds_s1;
+
+	srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+	srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 
 	printf("Board: %sRDB, ", cpu->name);
 	printf("Board rev: 0x%02x CPLD ver: 0x%02x, boot from ",
@@ -50,7 +55,40 @@ int checkboard(void)
 #endif
 
 	puts("SERDES Reference Clocks:\n");
-	printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
+	if (srds_s1 == 0x95)
+		printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
+	else
+		printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[0], freq[0]);
+
+	return 0;
+}
+
+static void board_mux_lane(void)
+{
+	ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 srds_prtcl_s1;
+	u8 reg = CPLD_READ(misc_ctl_status);
+
+	srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
+				FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+	srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+	if (srds_prtcl_s1 == 0x95) {
+		/* Route Lane B to PCIE */
+		CPLD_WRITE(misc_ctl_status, reg & ~CPLD_PCIE_SGMII_MUX);
+	} else {
+		/* Route Lane B to SGMII */
+		CPLD_WRITE(misc_ctl_status, reg | CPLD_PCIE_SGMII_MUX);
+	}
+	CPLD_WRITE(boot_override, CPLD_OVERRIDE_MUX_EN);
+}
+
+int board_early_init_f(void)
+{
+#if defined(CONFIG_DEEP_SLEEP)
+	if (is_warm_boot())
+		fsl_dp_disable_console();
+#endif
 
 	return 0;
 }
@@ -86,6 +124,7 @@ int board_early_init_r(void)
 #ifdef CONFIG_SYS_DPAA_QBMAN
 	setup_portals();
 #endif
+	board_mux_lane();
 
 	return 0;
 }
@@ -131,14 +170,3 @@ int ft_board_setup(void *blob, bd_t *bd)
 
 	return 0;
 }
-
-#ifdef CONFIG_DEEP_SLEEP
-void board_mem_sleep_setup(void)
-{
-	/* does not provide HW signals for power management */
-	CPLD_WRITE(misc_ctl_status, (CPLD_READ(misc_ctl_status) & ~0x40));
-	/* Disable MCKE isolation */
-	gpio_set_value(2, 0);
-	udelay(1);
-}
-#endif
diff --git a/board/freescale/t1040qds/ddr.c b/board/freescale/t1040qds/ddr.c
index 43f952f9c0..82402408a7 100644
--- a/board/freescale/t1040qds/ddr.c
+++ b/board/freescale/t1040qds/ddr.c
@@ -11,6 +11,7 @@
 #include <fsl_ddr_sdram.h>
 #include <fsl_ddr_dimm_params.h>
 #include <asm/fsl_law.h>
+#include <asm/mpc85xx_gpio.h>
 #include "ddr.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -100,6 +101,19 @@ found:
 #endif
 }
 
+#if defined(CONFIG_DEEP_SLEEP)
+void board_mem_sleep_setup(void)
+{
+	void __iomem *qixis_base = (void *)QIXIS_BASE;
+
+	/* does not provide HW signals for power management */
+	clrbits_8(qixis_base + 0x21, 0x2);
+	/* Disable MCKE isolation */
+	gpio_set_value(2, 0);
+	udelay(1);
+}
+#endif
+
 phys_size_t initdram(int board_type)
 {
 	phys_size_t dram_size;
@@ -112,5 +126,10 @@ phys_size_t initdram(int board_type)
 	dram_size *= 0x100000;
 
 	puts("    DDR: ");
+
+#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
+	fsl_dp_resume();
+#endif
+
 	return dram_size;
 }
diff --git a/board/freescale/t1040qds/eth.c b/board/freescale/t1040qds/eth.c
index 06d908658d..8c8293426b 100644
--- a/board/freescale/t1040qds/eth.c
+++ b/board/freescale/t1040qds/eth.c
@@ -18,6 +18,7 @@
 #include <fsl_mdio.h>
 #include <malloc.h>
 #include <asm/fsl_dtsec.h>
+#include <vsc9953.h>
 
 #include "../common/fman.h"
 #include "../common/qixis.h"
@@ -216,6 +217,7 @@ static void initialize_lane_to_slot(void)
 		lane_to_slot[1] = 7;
 		lane_to_slot[2] = 7;
 		lane_to_slot[3] = 7;
+		lane_to_slot[6] = 7;
 		lane_to_slot[7] = 7;
 		break;
 	case 0x8d:
@@ -438,6 +440,12 @@ int board_eth_init(bd_t *bis)
 #ifdef CONFIG_FMAN_ENET
 	struct memac_mdio_info memac_mdio_info;
 	unsigned int i;
+#ifdef CONFIG_VSC9953
+	int lane;
+	int phy_addr;
+	phy_interface_t phy_int;
+	struct mii_dev *bus;
+#endif
 
 	printf("Initializing Fman\n");
 	set_brdcfg9_for_gtx_clk();
@@ -477,6 +485,7 @@ int board_eth_init(bd_t *bis)
 	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
 		switch (fm_info_get_enet_if(i)) {
 		case PHY_INTERFACE_MODE_QSGMII:
+			fm_info_set_mdio(i, NULL);
 			break;
 		case PHY_INTERFACE_MODE_SGMII:
 			t1040_handle_phy_interface_sgmii(i);
@@ -491,6 +500,90 @@ int board_eth_init(bd_t *bis)
 		}
 	}
 
+#ifdef CONFIG_VSC9953
+	for (i = 0; i < VSC9953_MAX_PORTS; i++) {
+		lane = -1;
+		phy_addr = 0;
+		phy_int = PHY_INTERFACE_MODE_NONE;
+		switch (i) {
+		case 0:
+		case 1:
+		case 2:
+		case 3:
+			lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_A);
+			/* PHYs connected over QSGMII */
+			if (lane >= 0) {
+				phy_addr = CONFIG_SYS_FM1_QSGMII21_PHY_ADDR +
+						i;
+				phy_int = PHY_INTERFACE_MODE_QSGMII;
+				break;
+			}
+			lane = serdes_get_first_lane(FSL_SRDS_1,
+					SGMII_SW1_MAC1 + i);
+
+			if (lane < 0)
+				break;
+
+			/* PHYs connected over QSGMII */
+			if (i != 3 || lane_to_slot[lane] == 7)
+				phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR
+					+ i;
+			else
+				phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR;
+			phy_int = PHY_INTERFACE_MODE_SGMII;
+			break;
+		case 4:
+		case 5:
+		case 6:
+		case 7:
+			lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_B);
+			/* PHYs connected over QSGMII */
+			if (lane >= 0) {
+				phy_addr = CONFIG_SYS_FM1_QSGMII11_PHY_ADDR +
+						i - 4;
+				phy_int = PHY_INTERFACE_MODE_QSGMII;
+				break;
+			}
+			lane = serdes_get_first_lane(FSL_SRDS_1,
+					SGMII_SW1_MAC1 + i);
+			/* PHYs connected over SGMII */
+			if (lane >= 0) {
+				phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR
+						+ i - 3;
+				phy_int = PHY_INTERFACE_MODE_SGMII;
+			}
+			break;
+		case 8:
+			if (serdes_get_first_lane(FSL_SRDS_1,
+						  SGMII_FM1_DTSEC1) < 0)
+				/* FM1@DTSEC1 is connected to SW1@PORT8 */
+				vsc9953_port_enable(i);
+			break;
+		case 9:
+			if (serdes_get_first_lane(FSL_SRDS_1,
+						  SGMII_FM1_DTSEC2) < 0) {
+				/* Enable L2 On MAC2 using SCFG */
+				struct ccsr_scfg *scfg = (struct ccsr_scfg *)
+						CONFIG_SYS_MPC85xx_SCFG;
+
+				out_be32(&scfg->esgmiiselcr,
+					 in_be32(&scfg->esgmiiselcr) |
+					 (0x80000000));
+				vsc9953_port_enable(i);
+			}
+			break;
+		}
+
+		if (lane >= 0) {
+			bus = mii_dev_for_muxval(lane_to_slot[lane]);
+			vsc9953_port_info_set_mdio(i, bus);
+			vsc9953_port_enable(i);
+		}
+		vsc9953_port_info_set_phy_address(i, phy_addr);
+		vsc9953_port_info_set_phy_int(i, phy_int);
+	}
+
+#endif
 	cpu_eth_init(bis);
 #endif
 
diff --git a/board/freescale/t1040qds/t1040qds.c b/board/freescale/t1040qds/t1040qds.c
index 13285be42c..eaca57fc5d 100644
--- a/board/freescale/t1040qds/t1040qds.c
+++ b/board/freescale/t1040qds/t1040qds.c
@@ -19,8 +19,8 @@
 #include <asm/fsl_liodn.h>
 #include <fm_eth.h>
 #include <hwconfig.h>
-#include <asm/mpc85xx_gpio.h>
 
+#include "../common/sleep.h"
 #include "../common/qixis.h"
 #include "t1040qds.h"
 #include "t1040qds_qixis.h"
@@ -115,6 +115,16 @@ static void qe_board_setup(void)
 	}
 }
 
+int board_early_init_f(void)
+{
+#if defined(CONFIG_DEEP_SLEEP)
+	if (is_warm_boot())
+		fsl_dp_disable_console();
+#endif
+
+	return 0;
+}
+
 int board_early_init_r(void)
 {
 #ifdef CONFIG_SYS_FLASH_BASE
@@ -281,14 +291,3 @@ int board_need_mem_reset(void)
 {
 	return 1;
 }
-
-#ifdef CONFIG_DEEP_SLEEP
-void board_mem_sleep_setup(void)
-{
-	/* does not provide HW signals for power management */
-	QIXIS_WRITE(pwr_ctl[1], (QIXIS_READ(pwr_ctl[1]) & ~0x2));
-	/* Disable MCKE isolation */
-	gpio_set_value(2, 0);
-	udelay(1);
-}
-#endif
diff --git a/board/freescale/t104xrdb/MAINTAINERS b/board/freescale/t104xrdb/MAINTAINERS
index b61e1c0254..13d9be9da8 100644
--- a/board/freescale/t104xrdb/MAINTAINERS
+++ b/board/freescale/t104xrdb/MAINTAINERS
@@ -21,3 +21,4 @@ T1040RDB_SECURE_BOOT BOARD
 M:	Aneesh Bansal  <aneesh.bansal@freescale.com>
 S:	Maintained
 F:	configs/T1040RDB_SECURE_BOOT_defconfig
+F:	configs/T1042RDB_SECURE_BOOT_defconfig
diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c
index c8b6c672a6..7581a4cdd4 100644
--- a/board/freescale/t104xrdb/eth.c
+++ b/board/freescale/t104xrdb/eth.c
@@ -6,11 +6,13 @@
 
 #include <common.h>
 #include <netdev.h>
+#include <asm/fsl_serdes.h>
 #include <asm/immap_85xx.h>
 #include <fm_eth.h>
 #include <fsl_mdio.h>
 #include <malloc.h>
 #include <asm/fsl_dtsec.h>
+#include <vsc9953.h>
 
 #include "../common/fman.h"
 
@@ -20,6 +22,11 @@ int board_eth_init(bd_t *bis)
 	struct memac_mdio_info memac_mdio_info;
 	unsigned int i;
 	int phy_addr = 0;
+#ifdef CONFIG_VSC9953
+	phy_interface_t phy_int;
+	struct mii_dev *bus;
+#endif
+
 	printf("Initializing Fman\n");
 
 	memac_mdio_info.regs =
@@ -72,10 +79,58 @@ int board_eth_init(bd_t *bis)
 			fm_info_set_phy_address(i, 0);
 			break;
 		}
-		fm_info_set_mdio(i,
-				 miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
+		if (fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_QSGMII ||
+		    fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_NONE)
+			fm_info_set_mdio(i, NULL);
+		else
+			fm_info_set_mdio(i,
+					 miiphy_get_dev_by_name(
+							DEFAULT_FM_MDIO_NAME));
+	}
+
+#ifdef CONFIG_VSC9953
+	/* SerDes configured for QSGMII */
+	if (serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_A) >= 0) {
+		for (i = 0; i < 4; i++) {
+			bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
+			phy_addr = CONFIG_SYS_FM1_QSGMII11_PHY_ADDR + i;
+			phy_int = PHY_INTERFACE_MODE_QSGMII;
+
+			vsc9953_port_info_set_mdio(i, bus);
+			vsc9953_port_info_set_phy_address(i, phy_addr);
+			vsc9953_port_info_set_phy_int(i, phy_int);
+			vsc9953_port_enable(i);
+		}
+	}
+	if (serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_B) >= 0) {
+		for (i = 4; i < 8; i++) {
+			bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
+			phy_addr = CONFIG_SYS_FM1_QSGMII21_PHY_ADDR + i - 4;
+			phy_int = PHY_INTERFACE_MODE_QSGMII;
+
+			vsc9953_port_info_set_mdio(i, bus);
+			vsc9953_port_info_set_phy_address(i, phy_addr);
+			vsc9953_port_info_set_phy_int(i, phy_int);
+			vsc9953_port_enable(i);
+		}
 	}
 
+	/* Connect DTSEC1 to L2 switch if it doesn't have a PHY */
+	if (serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1) < 0)
+		vsc9953_port_enable(8);
+
+	/* Connect DTSEC2 to L2 switch if it doesn't have a PHY */
+	if (serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC2) < 0) {
+		/* Enable L2 On MAC2 using SCFG */
+		struct ccsr_scfg *scfg = (struct ccsr_scfg *)
+				CONFIG_SYS_MPC85xx_SCFG;
+
+		out_be32(&scfg->esgmiiselcr, in_be32(&scfg->esgmiiselcr) |
+			 (0x80000000));
+		vsc9953_port_enable(9);
+	}
+#endif
+
 	cpu_eth_init(bis);
 #endif
 
diff --git a/board/freescale/t4rdb/eth.c b/board/freescale/t4rdb/eth.c
index 142c6a877b..879bd1a347 100644
--- a/board/freescale/t4rdb/eth.c
+++ b/board/freescale/t4rdb/eth.c
@@ -101,7 +101,7 @@ int board_eth_init(bd_t *bis)
 	}
 
 #if (CONFIG_SYS_NUM_FMAN == 2)
-	if (srds_prtcl_s2 == 56) {
+	if ((srds_prtcl_s2 == 56) || (srds_prtcl_s2 == 55)) {
 		/* SGMII && XFI */
 		fm_info_set_phy_address(FM2_DTSEC1, SGMII_PHY_ADDR5);
 		fm_info_set_phy_address(FM2_DTSEC2, SGMII_PHY_ADDR6);
diff --git a/board/freescale/t4rdb/t4_rcw.cfg b/board/freescale/t4rdb/t4_rcw.cfg
index fdbbe5ef65..e46c7b25a5 100644
--- a/board/freescale/t4rdb/t4_rcw.cfg
+++ b/board/freescale/t4rdb/t4_rcw.cfg
@@ -1,7 +1,7 @@
 #PBL preamble and RCW header
 aa55aa55 010e0100
-#serdes protocol  27_56_1_9
+#serdes protocol  27_55_1_9
 16070019 18101916 00000000 00000000
-6c700848 00448c00 6c020000 f5000000
+6c6e0848 00448c00 6c020000 f5000000
 00000000 ee0000ee 00000000 000287fc
 00000000 50000000 00000000 00000028