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authorShengzhou Liu <Shengzhou.Liu@freescale.com>2015-04-22 10:59:50 +0800
committerYork Sun <yorksun@freescale.com>2015-05-04 09:25:12 -0700
commitfd3a78a538b2591a420f173faea442ae969ff623 (patch)
treec4552ab9843cfc935647a06264f8131dddb48350 /board/freescale
parent1a56fcea9f47ce9184f4dafd3e856de2d85d47cd (diff)
board/t2080rdb: reset cs4315 phy
CS4315 PHY doesn't support phy-reset by software, it needs to reset it by hardware via CPLD control. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board/freescale')
-rw-r--r--board/freescale/t208xrdb/cpld.h3
-rw-r--r--board/freescale/t208xrdb/t208xrdb.c7
2 files changed, 10 insertions, 0 deletions
diff --git a/board/freescale/t208xrdb/cpld.h b/board/freescale/t208xrdb/cpld.h
index 3f1533888d..9bd5247563 100644
--- a/board/freescale/t208xrdb/cpld.h
+++ b/board/freescale/t208xrdb/cpld.h
@@ -40,3 +40,6 @@ void cpld_write(unsigned int reg, u8 value);
#define CPLD_LBMAP_RESET 0xFF
#define CPLD_LBMAP_SHIFT 0x03
#define CPLD_BOOT_SEL 0x80
+
+/* RSTCON Register */
+#define CPLD_RSTCON_EDC_RST 0x04
diff --git a/board/freescale/t208xrdb/t208xrdb.c b/board/freescale/t208xrdb/t208xrdb.c
index ad393dfc5c..0c2c1c565b 100644
--- a/board/freescale/t208xrdb/t208xrdb.c
+++ b/board/freescale/t208xrdb/t208xrdb.c
@@ -107,6 +107,13 @@ unsigned long get_board_ddr_clk(void)
int misc_init_r(void)
{
+ u8 reg;
+
+ /* Reset CS4315 PHY */
+ reg = CPLD_READ(reset_ctl);
+ reg |= CPLD_RSTCON_EDC_RST;
+ CPLD_WRITE(reset_ctl, reg);
+
return 0;
}