diff options
| author | Tom Rini <trini@ti.com> | 2014-11-24 12:02:12 -0500 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2014-11-24 12:02:12 -0500 |
| commit | dee332ffb735f65ab922118791a583c17bb0b795 (patch) | |
| tree | d07bc0821792831aa4baeb27868252c2d32c7738 /board/gateworks/gw_ventana/clocks.cfg | |
| parent | 1739564e753bc3a8097f8937a3cbe738bdaaed5d (diff) | |
| parent | e7eb277dced570f177d75d56f40219d9dc599ed1 (diff) | |
Merge branch 'master' of git://www.denx.de/git/u-boot-imx
Diffstat (limited to 'board/gateworks/gw_ventana/clocks.cfg')
| -rw-r--r-- | board/gateworks/gw_ventana/clocks.cfg | 42 |
1 files changed, 0 insertions, 42 deletions
diff --git a/board/gateworks/gw_ventana/clocks.cfg b/board/gateworks/gw_ventana/clocks.cfg deleted file mode 100644 index a8118a258e..0000000000 --- a/board/gateworks/gw_ventana/clocks.cfg +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (C) 2013 Boundary Devices - * Copyright (C) 2013 Gateworks Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ - -/* set the default clock gate to save power */ -DATA 4, CCM_CCGR0, 0x00C03F3F -DATA 4, CCM_CCGR1, 0x0030FC03 -DATA 4, CCM_CCGR2, 0x0FFFC000 -DATA 4, CCM_CCGR3, 0x3FF00000 -DATA 4, CCM_CCGR4, 0xFFFFF300 /* enable NAND/GPMI/BCH clocks */ -DATA 4, CCM_CCGR5, 0x0F0000C3 -DATA 4, CCM_CCGR6, 0x000003FF - -/* enable AXI cache for VDOA/VPU/IPU */ -DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF -/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ -DATA 4, MX6_IOMUXC_GPR6, 0x007F007F -DATA 4, MX6_IOMUXC_GPR7, 0x007F007F - -/* - * Setup CCM_CCOSR register as follows: - * - * cko1_en = 1 --> CKO1 enabled - * cko1_div = 111 --> divide by 8 - * cko1_sel = 1011 --> ahb_clk_root - * - * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz - */ -DATA 4, CCM_CCOSR, 0x000000fb |