summaryrefslogtreecommitdiff
path: root/board/google/chromebook_coral/Kconfig
diff options
context:
space:
mode:
authorTom Rini <trini@konsulko.com>2019-12-18 07:20:19 -0500
committerTom Rini <trini@konsulko.com>2019-12-18 07:20:19 -0500
commitc0912f9bbfb26dd03d189953678691b799d35b6e (patch)
treef879600cd26b8d4678a174854b623941e5dc2ada /board/google/chromebook_coral/Kconfig
parent533c9f5714bdba79dc6f2629284d4c1a08a611d1 (diff)
parenta1d6dc3f84071f05574044f337dbdca70fae495d (diff)
Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-x86 into next
- Various x86 common codes updated for TPL/SPL - I2C designware driver updated for PCI - ICH SPI driver updated to support Apollo Lake - Add Intel FSP2 base support - Intel Apollo Lake platform specific drivers support - Add a new board Google Chromebook Coral
Diffstat (limited to 'board/google/chromebook_coral/Kconfig')
-rw-r--r--board/google/chromebook_coral/Kconfig43
1 files changed, 43 insertions, 0 deletions
diff --git a/board/google/chromebook_coral/Kconfig b/board/google/chromebook_coral/Kconfig
new file mode 100644
index 0000000000..940bee89b0
--- /dev/null
+++ b/board/google/chromebook_coral/Kconfig
@@ -0,0 +1,43 @@
+if TARGET_CHROMEBOOK_CORAL
+
+config SYS_BOARD
+ default "chromebook_coral"
+
+config SYS_VENDOR
+ default "google"
+
+config SYS_SOC
+ default "apollolake"
+
+config SYS_CONFIG_NAME
+ default "chromebook_coral"
+
+config SYS_TEXT_BASE
+ default 0xffe00000
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select X86_RESET_VECTOR
+ select INTEL_APOLLOLAKE
+ select BOARD_ROMSIZE_KB_16384
+
+config PCIE_ECAM_BASE
+ default 0xf0000000
+
+config EARLY_POST_CROS_EC
+ bool "Enable early post to Chrome OS EC"
+ help
+ Allow post codes to be sent to the Chroem OS EC early during boot,
+ to enable monitoring of the boot and debugging when things go wrong.
+ With this option enabled, the EC console can be used to watch post
+ codes the first part of boot.
+
+config SYS_CAR_ADDR
+ hex
+ default 0xfef00000
+
+config SYS_CAR_SIZE
+ hex
+ default 0xc0000
+
+endif