diff options
| author | Bin Meng <bmeng.cn@gmail.com> | 2014-12-17 15:50:38 +0800 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2014-12-18 17:26:06 -0700 |
| commit | b71eec3129c2626bfb1e98141b317d958e3cf384 (patch) | |
| tree | 960f136fd30d146892608b46f8eeff49c90c6f25 /board/google/chromebook_link | |
| parent | 0f61de8d9dba4ebfc4ea4b2da7f91adc937b3875 (diff) | |
x86: ich6-gpio: Add Intel Tunnel Creek GPIO support
Intel Tunnel Creek GPIO register block is compatible with current
ich6-gpio driver, except the offset and content of GPIO block base
address register in the LPC PCI configuration space are different.
Use u16 instead of u32 to store the 16-bit I/O address of the GPIO
registers so that it could support both Ivybridge and Tunnel Creek.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'board/google/chromebook_link')
| -rw-r--r-- | board/google/chromebook_link/link.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/board/google/chromebook_link/link.c b/board/google/chromebook_link/link.c index 4d95c1c927..9978e92006 100644 --- a/board/google/chromebook_link/link.c +++ b/board/google/chromebook_link/link.c @@ -125,7 +125,7 @@ int board_early_init_f(void) return 0; } -void setup_pch_gpios(u32 gpiobase, const struct pch_gpio_map *gpio) +void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio) { /* GPIO Set 1 */ if (gpio->set1.level) |