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authorPaul Burton <paul.burton@imgtec.com>2016-01-29 13:54:54 +0000
committerDaniel Schwierzeck <daniel.schwierzeck@gmail.com>2016-02-01 22:13:25 +0100
commit91ec615e5474e38bbd65f36b861849e70311548b (patch)
tree499281e95e4e5514dcc0311e76c749c1c99a6250 /board/imgtec/malta/malta.c
parent19a5ef60bb209f85ee2f61e99b65c321843b2316 (diff)
malta: Use I/O accessors for SuperI/O controller
Rather than passing the I/O port base address to the Super I/O code, switch it to using outb such that it makes use of the I/O port base address automatically. Drop the extern keyword to satisfy checkpatch whilst here. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Diffstat (limited to 'board/imgtec/malta/malta.c')
-rw-r--r--board/imgtec/malta/malta.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c
index 6f4aebc9c9..e31331aec1 100644
--- a/board/imgtec/malta/malta.c
+++ b/board/imgtec/malta/malta.c
@@ -130,26 +130,26 @@ void _machine_restart(void)
int board_early_init_f(void)
{
- void *io_base;
+ ulong io_base;
/* choose correct PCI I/O base */
switch (malta_sys_con()) {
case SYSCON_GT64120:
- io_base = (void *)CKSEG1ADDR(MALTA_GT_PCIIO_BASE);
+ io_base = CKSEG1ADDR(MALTA_GT_PCIIO_BASE);
break;
case SYSCON_MSC01:
- io_base = (void *)CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE);
+ io_base = CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE);
break;
default:
return -1;
}
- set_io_port_base((ulong)io_base);
+ set_io_port_base(io_base);
/* setup FDC37M817 super I/O controller */
- malta_superio_init(io_base);
+ malta_superio_init();
return 0;
}