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authorZubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>2016-07-29 15:11:20 +0100
committerDaniel Schwierzeck <daniel.schwierzeck@gmail.com>2016-09-21 14:55:14 +0200
commitebf2b9e3dff089a9c99e5dc8d7e10b06365e4e46 (patch)
tree157ecc4b0f703325670acc961179e29f05989f9a /board/imgtec/xilfpga/xilfpga.c
parentd4e85377e79f52172c1df7469bf7d56ab0a85322 (diff)
mips: Add MIPSfpga platform support
MIPSfpga is an FPGA based dev platform. In a nutshell, its a microAptiv cpu core with lots of Xilinx IP blocks The FPGA dev board used is the Nexys4DDR board by Digilent. For more information, check the Readme file in board/imgtec/xilfpga Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Diffstat (limited to 'board/imgtec/xilfpga/xilfpga.c')
-rw-r--r--board/imgtec/xilfpga/xilfpga.c20
1 files changed, 20 insertions, 0 deletions
diff --git a/board/imgtec/xilfpga/xilfpga.c b/board/imgtec/xilfpga/xilfpga.c
new file mode 100644
index 0000000000..77a1952c93
--- /dev/null
+++ b/board/imgtec/xilfpga/xilfpga.c
@@ -0,0 +1,20 @@
+/*
+ * Imagination Technologies MIPSfpga platform code
+ *
+ * Copyright (C) 2016, Imagination Technologies Ltd.
+ *
+ * Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+
+#include <common.h>
+
+/* initialize the DDR Controller and PHY */
+phys_size_t initdram(int board_type)
+{
+ /* MIG IP block is smart and doesn't need SW
+ * to do any init */
+ return CONFIG_SYS_SDRAM_SIZE; /* in bytes */
+}